International Business Machines Corporation

Samsung Electronics Co., Ltd.

Globalfoundries Inc.

Eth Zurich

Tomas Tuma

Abu Sebastian

Angeliki Pantazi

Evangelos Stavros Eleftheriou

Manuel Le Gallo

Manuel Le Gallo-Bourdeau

Paul T Hurley

Lukas Kull

Wabe W Koelmans

Timoleon Moraitis

Irem Boybat Kara

Nikolaos Papandreou

Mark Alfred Lantz

John G Rooney

Konstantinos Bekas

Alessandro Curioni

Milos Stanisavljevic

Patrick Droz

Stanislaw Andrzej Wozniak

Sean G Rooney

John Lygeros

Walter E M Haeberle

A circuit implementing a spiking neural network that includes a learning component that can learn from temporal correlations in the spikes regardless of correlations in the rates. In some embodiments, the learning component comprises a rate-discounting component. In some embodiments, the learning rule computes a rate-normalized covariance (normcov) matrix, detects clusters in this matrix, and sets the synaptic weights according to these clusters. In some embodiments, a synapse with a long-term plasticity rule has an efficacy that is composed by a weight and a fatiguing component. In some embodiments, A Hebbian plasticity component modifies the weight component and a short-term fatigue plasticity component modifies the fatiguing component. The fatigue component increases with increases in the presynaptic spike rate. In some embodiments, the fatigue component increases are implemented in a spike-based manner. In some embodiments, the Hebbian plasticity is a spike-timing-dependent plasticity (STDP), resulting in a fatiguing STDP (FSTDP) synapse.

STDP with synaptic fatigue for learning of spike-time-coded patterns in the presence of parallel rate-coding

Artificial neuron apparatus includes first and second resistive memory cells. The first resistive memory cell is connected in first circuitry having a first input and output. The second resistive memory cell is connected in second circuitry having a second input and output. The first and second circuitry are operable in alternating read and write phases to apply a programming current to their respective memory cells on receipt of excitatory and inhibitory neuron input signals, respectively. During the write phase, resistance of the respective cells is changed in response to successive excitatory and inhibitory neuron input signals. During the read phase, a read current is applied to their respective cells to produce first and second measurement signals, respectively. An output circuit connected to the first and second outputs produces a neuron output signal at a neuron output when a difference between the first and second measurement signals traverses a threshold.

Artificial neuron apparatus

A method and system providing a multi-memristive synaptic element for a cognitive computing system. The multi-memristive synaptic element comprises an array of memristive devices. The method comprises arbitrating a synaptic weight allocation, a related synaptic weight being represented by a synaptic weight variable of said multi-memristive synaptic element, updating said synaptic weight variable by a delta amount, and assigning said memristive devices to elements of a clock-like ordered circular list for selecting a particular memristor of said memristive devices requiring to be updated by a deterministic, periodic global clock that points to a different memristor at every clock tick, such that said multi-memristive synaptic element has a larger dynamic range and a more linear conductance response than a single memristor synaptic element.

Multi-memristive synapse with clock-arbitrated weight update

A resistive memory cell is connected in circuitry which has a first input terminal for applying neuron input signals including a read portion and a write portion. The circuitry includes a read circuit producing a read signal dependent on resistance of the memory cell, and an output terminal providing a neuron output signal, dependent on the read signal in a first state of the memory cell. The circuitry also includes a storage circuit storing a measurement signal dependent on the read signal, and a switch set operable to supply the read signal to the storage circuit during application of the read portion of each neuron input signal to the memory cell, and, after application of the read portion, to apply the measurement signal in the apparatus to enable resetting of the memory cell to a second state.

This invention relates to an apparatus, system, and method for computing with neuromorphic circuit architectures that have neurons with interconnected internal state information. The interconnected internal state information allows the neurons to enable or strengthen the input to other neurons. Furthermore, neuron internal state information provides insights on the characteristics of the input data that can be used to enhance the performance of the neuromorphic system. The neuromorphic system can be implemented with an artificial phase-change-based neurons.

Neuromorphic architecture with multiple coupled neurons using internal state neuron information

A sensor arrangement for position sensing comprises a magnetic field source and a magnetoresistive element arranged in a magnetic field generated by the magnetic field source, which magnetoresistive element provides an output signal (R) dependent on a position (x) of the magnetoresistive element relative to the magnetic field source. A feedback controller is configured to receive the output signal (R) of the magnetoresistive element and is configured to adjust one or more of the position (x) of the magnetoresistive element relative to the magnetic field source and a strength of the magnetic field generated by the magnetic field source acting on the magnetoresistive element dependent on the output signal (R) of the magnetoresistive element.

Sensor arrangement for position sensing

A neuromorphic synapse with a resistive memory cell connected in circuitry having first and second input terminals. The input terminals respectively receive pre-neuron and post-neuron action signals, each having a read portion and a write portion, in use. The circuitry includes an output terminal for providing a synaptic output signal which is dependent on resistance of the memory cell. The circuitry is configured such that the synaptic output signal is provided at the output terminal in response to application at the first input terminal of the read portion of the pre-neuron action signal, and such that a programming signal, for programming resistance of the memory cell, is applied to the cell in response to simultaneous application of the write portions of the pre-neuron and post-neuron action signals at the first and second input terminals respectively. The synapse can be adapted for operation with identical pre-neuron and post-neuron action signals.

Neuromorphic synapses

Artificial neuron apparatus includes a resistive memory cell connected in an input circuit having a neuron input, for receiving neuron input signals, and a current source for supplying a read current to the cell. The input circuit is selectively configurable in response to a set of control signals, defining alternating read and write phases of operation, to apply the read current to the cell during the read phase and to apply a programming current to the cell, for programming cell resistance, on receipt of a neuron input signal during the write phase. The cell resistance is progressively changed from a first state to a second state in response to successive neuron input signals. The apparatus further includes an output circuit comprising a neuron output and a digital latch which is connected to the input circuit for receiving a measurement signal dependent on cell resistance.

A neuromorphic processing device has a device input, for receiving an input data signal, and an assemblage of neuron circuits. Each neuron circuit comprises a resistive memory cell which is arranged to store a neuron state, indicated by cell resistance, and to receive neuron input signals for programming cell resistance to vary the neuron state, and a neuron output circuit for supplying a neuron output signal in response to cell resistance traversing a threshold. The device includes an input signal generator, connected to the device input and the assemblage of neuron circuits, for generating neuron input signals for the assemblage in dependence on the input data signal. The device further includes a device output circuit, connected to neuron output circuits of the assemblage, for producing a device output signal dependent on neuron output signals of the assemblage, whereby the processing device exploits stochasticity of resistive memory cells of the assemblage.

Neuromorphic processing devices

A computing system includes computational memory and digital combinational circuitry operatively coupled with the computational memory. The computational memory is configured to perform computations at a prescribed precision. The digital combinational circuitry is configured to increase the precision of the computations performed by the computational memory. The computational memory and the digital combinational circuitry may be configured to iteratively perform a computation to a predefined precision. The computational memory may include circuitry configured to perform analog computation using values stored in the computational memory, and the digital combinational circuitry may include a central processing unit, a graphics processing unit and/or application specific circuitry. The computational memory may include an array of resistive memory elements having resistance or conductance values stored therein, the respective resistance or conductance values being programmable.

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Adliswil, Switzerland

Tomas Tuma