Qualcomm Incorporated

Maxlinear, Inc.

Tomas O'Sullivan

Jianjun Yu

Lai Kan Leung

Yiwu Tang

Dongmin Park

Yue Chao

Alvin Siu-Chi Li

Dongling Pan

Richard Chang

Brian James Kaczynski

Cristian Marcu

Heui In Yoon

Methods and apparatus for storing a control voltage of a phased-locked loop (PLL) when switching from mission mode to standby mode for the PLL, and for restoring the control voltage of the PLL when switching back to mission mode. An example PLL circuit includes a charge pump, a voltage-controlled oscillator (VCO) having a control input coupled to an output of the charge pump via a node, and a tracking circuit coupled to the node. The tracking circuit is generally configured to sample a voltage of the node during a mission mode, save a representation of the sampled voltage before entering a standby mode, and restore the sampled voltage to the node for reentering the mission mode using the saved representation of the sampled voltage.

Tuning voltage tracker for receive/transmit phase-locked loop (PLL) fast switching

An aspect relates to an apparatus including an input buffer including an input configured to receive an input voltage; a ramp voltage generator including an input coupled to an output of the input buffer; an evaluation circuit including an input coupled to an output of the ramp voltage generator, wherein the evaluation circuit includes a first resistor coupled in series with first field effect transistor (FET) between a first voltage rail and a second voltage rail; and an output buffer including an input coupled to a drain of the first FET and an output configured to generate an output voltage.

Low power digital-to-time converter (DTC) linearization

A method of quantization noise cancellation in a phase-locked loop (PLL) is provided according to certain aspects. The PLL includes a phase detector having a first input configured to receive a reference signal and a second input configured to receive a feedback signal. The method includes delaying the reference signal by a first time delay, delaying the feedback signal by a second time delay, receiving a delta-sigma modulator (DSM) error signal, and adjusting the first time delay and the second time delay in opposite directions based on the DSM error signal.

Differential digital-to-time converter for even-order INL cancellation and supply noise/disturbance rejection

A frequency synthesizer system may include a first voltage-controlled oscillator (VCO) circuit, a second VCO circuit, and multiplexing circuitry. The multiplexing circuitry may be configured to select either the output of the first VCO circuit or the output of the second VCO circuit in response to a mode selection signal.

Frequency synthesizer with selectable modes

A clock generator includes, in part, a buffer, a peak detector and a control logic. The buffer generates a clock output signal in response to receiving a clock signal and a feedback signal that controls the gain of the buffer. If the peak detector detects that the amplitude of the output signal is higher than the upper bound of the predefined range, the gain value applied to the variable buffer is decreased. If the peak detector detects that the amplitude of the output signal is lower than the lower bound of the predefined range, the gain value applied to the variable buffer to increased. If the peak detector detects that the amplitude of the output signal is within the predefined range, no change is made to the gain value applied to the variable buffer. The control logic generates the feedback signal in response to the peak detector's output signal.

Clock-out amplitude calibration scheme to ensure sine-wave clock-out signal

A frequency synthesizer for a WLAN transceiver is disclosed that may be used to generate 5.4 GHz and 2.4 GHz signals. The frequency synthesizer may be configured to minimize VCO pulling by using VCO operating frequencies that are not integer multiples of the RF bands. Further, the frequency synthesizer may be configured to minimize interference with other frequency bands used by existing wireless systems.

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San Diego, CA, United States of America

Tomas O'Sullivan