Synopsys, Inc.

Nxp B.v.

Tomas Henriksson

Elisabeth Francisca Maria Steffens

Martijn Coenen

Elisabeth Steffens

Pieter Van Der Wolf

The present invention relates to the implementation for implementing multi-tasking on a digital signal processor. For that purpose blocking functions are arranged such that they do not make use of a processor's hardware stack. Respective function calls are replaced with a piece of inline assembly code, which instead performs a branch to the correct routine for carrying out said function. If a blocking condition of the blocking function is encountered, a task switch can be done to resume another task. While the hardware stack is not used when a task switch might have to occur, mixed-up contents of the hardware stack among function calls performed by different tasks are avoided.

Implementation of multi-tasking on a digital signal processor with a hardware stack

The present invention discloses an integrated circuit arrangement () comprising a data communication network comprising a plurality of connections (), a plurality of modules () coupled to the data communication network via at least one network interface (), the network interface comprising a plurality of buffers; a remote service module () being coupled to the data communication network via a further network interface (), wherein each of said modules () is arranged to provide its network interface () with a service request () for the remote service module (), said network interface being arranged to extend said service request with a first identifier () for establishing a network connection () with a remote service module (); and a circuit portion () comprising a plurality of buffers () between the at least one network interface () and the remote service module () for storing service requests () from the plurality of modules (), said circuit portion comprising decoding logic () for selecting one of said buffers () by decoding a further identifier () embedded in the service request ().

Integrated circuit arrangement for buffering service requests

The disclosure relates to the implementation of multi-tasking on a digital signal processor. Blocking functions are arranged such that they do not make use of a processor's hardware stack. Respective function calls are replaced with a piece of inline assembly code, which instead performs a branch to the correct routine for carrying out said function. If a blocking condition of the blocking function is encountered, a task switch can be done to resume another task. Whilst the hardware stack is not used when a task switch might have to occur, mixed-up contents of the hardware stack among function calls performed by different tasks are avoided.

A resource controller that includes a first buffer configured to store requests of a first predefined category having a first priority. In addition, the resource controller includes at least a second buffer configured to store requests of a second predefined category having a second priority where the first priority is set such that processing requests of the first category has priority over processing the requests of the second category. Also, the resource controller includes a mechanism configured to block the requests of the first category when a predefined condition is met.

Systems and methods for resource controlling

The present application relates to a method for resource controlling comprising controlling the processing of requests of a first category having a first priority. The method comprises controlling the processing of requests of a second category having a second priority, wherein the first priority is set such that processing the requests of the first category has priority over processing the requests of the second category. The method comprises blocking requests of the first category by a mechanism that detects when a predefined condition regarding the service provided to the second category is met.

Resource controlling with dynamic priority adjustment

The invention relates to a memory controller for use in a System-on-Chip, wherein the System-on-Chip comprises a plurality of agents and an off-chip volatile memory. The memory controller comprises a first port (CBP) for receiving low-priority requests (CBR) for access to the volatile memory from a first-subset of the plurality of agents and a second port (LLP) for receiving high-priority requests (LLR) for access to the volatile memory from a second-subset of the plurality of agents, wherein the memory controller is configured for arbitrating between the high-priority requests (LLR) and the low-priority requests (CBR), wherein the memory controller is configured for receiving refresh requests (RFR) for the volatile memory via the first port (CBP), wherein the refresh requests (RFR) are time-multiplexed with the low-priority requests (CBR), wherein the memory controller is configured for treating the low-priority requests (CBR) and the refresh requests (RFR) the same. The effect is that the arbitration between the different requests is rendered less complex. In embodiments of the memory controller there is also an average latency reduction for the high-priority requests. The invention further relates to a System-on-Chip comprising the memory controller, to a method of a refresh request generator for use in such System-on-Chip. The invention also relates to a method of controlling access of a System-on-Chip to a volatile memory, wherein the System-on-Chip comprises a plurality of agents which need access to the volatile memory, and to a computer program product comprising instructions for causing a processor to perform such method.

Memory controller with external refresh mechanism

Requests from a plurality of different agents () are passed to a request handler via a request concentrator. In front of the request concentrator the requests are queued in a plurality of queues (). A first one of the agents is configured to issue a priority changing command with a defined position relative to pending requests issued by the first one of the agents () to the first one of the queues (). An arbiter (), makes successive selections selecting queues () from which the request concentrator () will pass requests to the request handler (), based on relative priorities assigned to the queues (). The arbiter () responds to the priority changing command by changing the priority of the first one of the queues (), selectively for a duration while the pending requests up to the defined position are in the first one of the queues (). Different queues may be provided for read and write requests from the first one of the agents. In this case, the priority raising request from the agent may be used to raise the priority level of the write queue temporarily to the level of the read queue, until all write requests issued before the priority raising command from the agent have been passed to the request handler.

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Sollentuna, Sweden

Tomas Henriksson