Hewlett-packard Company

Hewlett-packard Development Company, L.p.

Tomas G Rokicki

Rajiv Gupta

Gadiel Seroussi

Ludmila Cherkasova

Marcelo Weinberger

Robert Bruce Aglietti

Neri Merhav

Joesp M Ferrandiz

A system and method for controlling the scheduling of threads in a multi-thread processor system. The multi-thread processor system has a multi-thread processor, a main memory, a cache memory, and a thread scheduler. Information is sent from the cache memory to the thread scheduler for determining which thread the processor is going to execute. The thread scheduler calculates or maintains a figure of merit for each thread executing on the processor. The figure of merit determines which thread to switch to when the current or previous thread has a long latency. The figure of merit define the execution environment as measured by the performance of the cache memory. The figure of merit can be the owner of a particular thread, the number of data lines accessed by a particular thread which resides in the cache, the number of times a particular thread has hit in the cache over a specified time interval, the thread that installed the data or the thread that was used most recently.

Multi-threaded processing system and method for scheduling the execution of threads based on data received from a cache memory

Optimizing computer performance by using data compression principles to minimize a loss function

The present invention provides a method and an apparatus for addressing a main memory unit in a computer system which results in improved page hit rate and reduced memory latency by only keeping open some recently used pages and speculatively closing the rest of the pages in the main memory unit. In a computer system with 64 banks and 2 CPUs, only 8 banks may be kept open and the remaining 56 banks are kept closed. Keeping only 8 banks open will not reduce the page hit frequency significantly, but will allow most accesses that are not page hits to access banks that are already closed, so that they are not slowed down by open banks. Thus, the page hit rate is increased and the miss rate is reduced.

Method and computer system for speculatively closing pages in memory

A method, system, and apparatus for improving performance of a program executing on a computer system. More particularly the present invention improves the balance determined by an ordering of information stored in a tree-based data structure on a computer thereby reducing the time required to search, update, or perform other common operations on the tree-based data structure.

Method, system, and apparatus to improve performance of tree-based data structures in computer programs

A method for operating a server on a computer network to supply data stored on the server in response to requests received on the network. The server stores the requests in a queue and determines a priority value for the request. The priority value includes the sum of a counter value and a cost value, the cost value being monotonically related to the quantity of server resources needed to service the request. When the server selects one of the requests stored in the queue for servicing it picks the request having the lowest priority value of the requests stored in the queue. The selected request is removed from the queue and the counter value is incremented by a value proportional to the cost value associated with the request selected for servicing. In one embodiment, the cost value is proportional to the length of a file specified in the received request. In one embodiment, one of the received requests also includes information specifying a class for the request. The server also determines a maximum priority value for that class, the maximum priority value being at least as great as the priority value having the highest value for any request of that class currently stored in the queue. The server compares the determined priority value for the received request with the maximum priority value and changes the determined priority value to a value greater than the maximum value if the determined priority value was less than or equal to the maximum priority value.

Scheduling server requests to decrease response time and increase server

A main memory indexing scheme optimizes consecutive page hits in computer systems having a main memory system and a cache memory. In accordance with the present invention, one or more bank select bits required by the main memory system are formed from one or more of the address bits that are used by the cache memory as the tag field. Preferably, the lower-order bits of the tag field are used. To increase the page hit rate even further, additional bank select bits are formed from the address bits immediately above the bits used to access columns. In one embodiment of the present invention, address bits are simply mapped to bank bits using a one-to-one correspondence. In another embodiment, address bits from the tag field and address bits immediately above the column bits are combined using a function such as an exclusive-OR operation or an addition operation, with the result of the function provided to the bank select bits. The present invention greatly improves the page hit rate of computer systems, while requiring few additional resources.

Growing community of inventors

Palo Alto, CA, United States of America

Tomas G Rokicki