The Royal Institution for the Advancement of Learning / Mcgill University

Pmc-sierra, Inc.

Pmc-sierra Us, Inc.

Microsemi Storage Solutions (u.s.), Inc.

Tomas A Dusatko

Frederic Nabki

Mourad El-Gamal

William Michael Lye

Predrag Acimovic

Vadim Milirud

Srikar Vengallatore

A hybrid analog-digital, dual path, delta-sigma modulator (DSM) based fractional-N phase-lock-loop (PLL) that includes an integral path and a proportional path is provided. The integral path is implemented in the digital domain. The proportional path may be implemented in either the digital or analog domain. A feed-forward error correction signal generator is used to generate a feed-forward signal for attenuating in-band spurs generated by the quantization error of the integral path phase detector.

Digital correction of spurious tones caused by a phase detector of a hybrid analog-digital delta-sigma modulator based fractional-N phase locked loop

Methods and apparatus improve the signal integrity of high-speed integrated circuits. Disclosed is a passive network for an input to a receiver. One embodiment of the passive network has two coupled inductors to improve both return loss and insertion loss characteristics. A shunt inductor is connected in series with the termination resistance, while a series inductor is placed in series between the pad and receiver circuitry. By exploiting deliberately-introduced mutual coupling between these two inductors, an area-efficient passive network is created that improves both the return loss and input bandwidth.

Method and apparatus for improving the signal integrity of high-speed serial data receivers using coupled inductors

A method and apparatus for interleaving high-speed, delta-sigma based over-sampled DACs. A delta-sigma modulator is decomposed into a parallel poly-phase block-filter running at a lower rate. The generated parallel digital data is then fed directly to the analog DAC output stage where it is directly combined to form the full-rate signal using a 1-hot-of-N output stage. By using a poly-phase implementation, the complexity of the high-speed parallel digital-analog timing interface is simplified, along with the timing requirements of the delta-sigma modulator which normally would have to run at the full-oversampled rate. The 1-hot-of-N signal encoding is directly generated from the parallel delta-sigma modulator, and efficiently encodes the data in such a way to minimize signal-dependent supply noise. The architecture disclosed is advantageous for the practical implementation of high-speed over-sampled DACs, such as those used in stringent wireless applications.

Interleaved digital to analog conversion

A method for manufacturing microelectromechanical structures (MEMS) is disclosed. A low temperature MEMS device is designed. The low temperature MEM device is based upon a semiconductor manufacturing process comprising at least one semiconductor process for providing at least a heater therein. Each semiconductor process used in implementing the design is limited to a maximum temperature of the in-process low temperature MEMs device or a substrate onto which the low temperature MEMS device is being manufactured to below 300&#xb0; C.

Direct contact heat control of micro structures

A method of providing microelectromechanical structures (MEMS) that are compatible with silicon CMOS electronics is provided. The method provides for processing and manufacturing is steps limiting a maximum exposure of an integrated circuit upon which the MEMS is manufactured during MEMS manufacturing to below a temperature wherein CMOS circuitry is adversely affected, for example below 400&#xb0; C., and sometimes to below 300&#xb0; C. or 250&#xb0; C., thereby allowing direct manufacturing of the MEMS devices onto electronic integrated circuits, such as Si CMOS circuits.

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Vancouver, Canada

Tomas A Dusatko