Xilinx, Inc.

Xlnx, Inc.

Tomai Knopp

Ahmad R Ansari

Sarosh Azad

Sagheer Ahmad

Bhaarath Kumar

Bradley L Taylor

Khang Kim Dao

Jeffrey H Seltzer

Roger D Flateau, Jr

Alex Scott Warshofsky

Sanford L Helton

Kam-Wing Li

Banadappa V Shivaray

Pranjal Chauhan

Pramod Surathkal

Soumitra Kumar Bhowmick

Benson Chau

An integrated circuit (IC) for clock and phase aligning and synchronization between physical (PHY) layers and a communications controller is provided. The IC includes a clock multiplier configured to multiply a frequency of the clock signal from a plurality of PHY layers to match a frequency of a clock signal of the controller, wherein the clock signal from the plurality of PHY layers is less than the frequency of the clock signal of the controller. IC support circuitry is configured to provide the multiplied clock signal to the controller. The IC includes a first clock divider configured to divide the frequency of the multiplied clock signal and to output the divided clock signal to the controller. The IC includes a phase alignment circuit configured to align phases of one or more data signals based on a phase of the clock signal and a phase of the multiplied clock signal.

Clock and phase alignment between physical layers and controller

A system is disclosed that includes a first communication circuit that communicates data over a first data port using a first communication protocol. The system also includes a second communication circuit that communicates data over a second data port using a second communication protocol. The second communication protocol processes read and write requests in an order that the read and write requests are received. A bridge circuit is configured to communicate data between the first data port of the first communication circuit and the second data port of the second communication circuit. The bridge circuit is configured to communicate non-posted writes to the second communication circuit via a buffer circuit and communicate posted writes to the second communication circuit via a communication path that bypasses the buffer circuit.

Methods and circuits for deadlock avoidance

A device includes a plurality of memory components with redundant columns associated therewith, a sub-block controller, and a volatile memory. The sub-block controller generates a repair vector, during manufacture testing mode. The repair vector is associated with the plurality of memory components and is generated responsive to detecting a defect within a column of the plurality of memory components. No repair vector is generated responsive to detecting no defect within a column of the plurality of memory components. The volatile memory receives and stores the repair vector in a nonvolatile memory component, during the manufacture testing mode. The volatile memory receives the repair vector from the nonvolatile memory component if the repair vector was generated during the manufacture testing mode, at startup mode, and provides it to the sub-block controller. The sub-block controller loads a repair data into the plurality of memory components based on the repair vector.

Distributed memory repair network

Embodiments herein describe a methodology for performing non-destructive LBIST when booting an integrated circuit (IC). In one embodiment, when powered on, the IC begins the boot process (e.g., a POST) which is then paused to perform LBIST. However, instead of corrupting or destroying the boot mode state of the IC, the LBIST is non-destructive. That is, after LBIST is performed, the booting process can be resumed in the same state as when LBIST began.

Non-destructive online testing for safety critical applications

The disclosure describes a circuit arrangement that includes a master circuit and a slave circuit. The master circuit generates transactions, and the slave circuit generates responses to the transactions from the master circuit. A first circuit is coupled between the master circuit and the slave circuit. The first circuit determines for each transaction from the master circuit whether the slave circuit generates an expected number of responses within a timeout period. For each transaction for which the slave circuit does not generate the expected number of responses within the timeout period, the first circuit generates and transmits the expected number of responses to the master circuit.

Circuit arrangement with transaction timeout detection

A method for operating a programmable IC is disclosed. A set of circuits specified by a set of configuration data is operated in a set of programmable resources. In response to one of a set of status signals indicating an error, a value indicative of an error is stored in a respective one of a plurality of error status registers. The values stored in the plurality of error status registers are provided to an error handling circuit included in the set of circuits specified by the set of configuration data and operated in the programmable resources. At least one error handling process is performed by the error handling circuit as a function of values stored in the plurality of error status registers.

User-configurable error handling

An apparatus for communication using a master-slave communication protocol includes a master circuit and a slave circuit configured to communicate with each other using a master-slave communication protocol. The apparatus also includes an interface circuit coupled to the master and slave circuits. In response to a first control signal having a first value, the interface circuit forwards messages received from the master circuit to the slave circuit and forwards responses received from the slave circuit to the master circuit. In response to the first control signal having a second value, the interface circuit prevents messages received from the master circuit from being forwarded from the master circuit to the slave circuit.

Isolation interface for master-slave communication protocols

A circuit for realigning data received at a receiver is disclosed. The circuit comprises a plurality of memory arrays; a plurality of multiplexers, wherein each multiplexer is coupled to select an address for data to be output by a memory array of the plurality of memory arrays; an output multiplexer coupled to select the outputs of the plurality of memory arrays; and a memory control circuit coupled to the plurality of multiplexers and the output multiplexer, the memory control circuit coupling select signals to the plurality of multiplexers and the output multiplexer to enable generating realigned data. A method of realigning data received at a receiver is also disclosed.

Circuit for and method of realigning data at a receiver

A method of bridging a plurality of buses within a bus bridge can include determining whether a queue of the bus bridge includes a transaction request directed to a restricted address range and, for each received transaction request, determining whether an address to which the transaction request is directed is within the restricted address range. Each transaction request received by the bus bridge can be selectively rejected according to whether the address to which the transaction request is directed is within the restricted address range and whether the queue includes a transaction request directed to the restricted address range.

Deadlock-resistant bus bridge with pipeline-restricted address ranges

A circuit for transmitting a block of data is disclosed. The circuit comprises a memory array having a plurality of memory locations coupled to receive data; a first data source coupled to the memory array, wherein data from the first data source is stored at sequential addressable memory locations of the plurality of memory locations on a first in, first out basis; a second data source coupled to the memory array, the second data source providing data to be stored in a predetermined memory location of the sequential addressable memory locations storing data from the second data source; and a selection circuit coupled to the first data source and the second data source for selecting data to be stored in the plurality of memory locations.

Growing community of inventors

San Jose, CA, United States of America

Tomai Knopp