Headway Technologies, Incorporated

Taiwan Semiconductor Manufacturing Comp. Ltd.

Magic Technologies, Inc.

Applied Spintronics, Inc.

Advanced Numicro Systems, Inc.

Tom Zhong

Jesmin Haq

Zhongjian Teng

Chyu-Jiuh Torng

Rongfu Xiao

Wai-Ming Johnson Kan

Adam Zhong

Vinh Lam

Yi Yang

Witold Kula

Vignesh Sundar

Yu-Jen Wang

Liubo Hong

Dongna Shen

Wei Cao

Daniel H Liu

Terry Kin Ting Ko

Ru-Ying Tong

Cheng Tzong Horng

Kenlin Huang

Chyu-Jinh Torng

Min Li

Kunliang Zhang

Lin Yang

Sahil Patel

Jianing Zhou

Ruhang Ding

Rodolfo Belen

Hiroshi Omine

Po-Kang Wang

Yee-Chung Fu

Luc Thomas

Guomin Mao

Jun Chen

An STT-MRAM device incorporating a multiplicity of MTJ junctions is encapsulated so that it dissipates heat produced by repeated read/write processes and is simultaneously shielded from external magnetic fields of neighboring devices. In addition, the encapsulation layers can be structured to reduced top lead stresses that have been shown to affect DR/R and Hc. We provide a device design and its method of fabrication that can simultaneously address all of these problems.

STT-MRAM heat sink and magnetic shield structure design for more robust read/write performance

A plurality of conductive via connections are fabricated on a substrate located at positions where MTJ devices are to be fabricated, wherein a width of each of the conductive via connections is smaller than or equivalent to a width of the MTJ devices. The conductive via connections are surrounded with a dielectric layer having a height sufficient to ensure that at the end of a main MTJ etch, an etch front remains in the dielectric layer surrounding the conductive via connections. Thereafter, a MTJ film stack is deposited on the plurality of conductive via connections surrounded by the dielectric layer. The MTJ film stack is etched using an ion beam etch process (IBE), etching through the MTJ film stack and into the dielectric layer surrounding the conductive via connections to form the MTJ devices wherein by etching into the dielectric layer, re-deposition on sidewalls of the MTJ devices is insulating.

Etching and encapsulation scheme for magnetic tunnel junction fabrication

Systems and methods for controlling a critical dimension (CD) uniformity of a magnetic head device are described. A film stack that is part of a system for controlling a critical dimension (CD) uniformity of a magnetic head device can include a substrate, a magnetoresistive (MR) sensor layer, and a hard mask layer. The system can also include a first mask that defines critical shape patterns other than the CD. The hard mask layer can be patterned using the first mask. The system can also include a second mask that defines the CD. A mandrel pattern can be formed on the hard mask layer using the second mask.

System for controlling a critical dimension (CD) uniformity of a magnetic head device

A magnetic tunneling junction (MTJ) structure is described. The MJT structure includes a stress modulating layer on a first electrode layer, where a material of the stress modulating layer is different from a material of the first electrode layer. The MJT structure further includes a MTJ material stack on the stress modulating layer. And the MJT structure further includes a second electrode layer on the MTJ material stack. The stress modulating layer reduces crystal growth defects and interfacial defects during annealing and improve the interface lattice epitaxy. This will improve device performance.

MTJ device performance by adding stress modulation layer to MTJ device structure

A layered thin film device, such as a MTJ (Magnetic Tunnel Junction) device can be customized in shape by sequentially forming its successive layers over a symmetrically curved electrode. By initially shaping the electrode to have a concave or convex surface, the sequentially formed layers conform to that shape and acquire it and are subject to stresses that cause various crystal defects to migrate away from the axis of symmetry, leaving the region immediately surrounding the axis of symmetry relatively defect free. The resulting stack can then be patterned to leave only the region that is relatively defect free.

MTJ device performance by controlling device shape

A three terminal spin-orbit-torque (SOT) device is disclosed wherein a free layer (FL) with a switchable magnetization is formed on a Spin Hall Effect (SHE) layer comprising a Spin Hall Angle (SHA) material. The SHE layer has a first side contacting a first bottom electrode (BE) and an opposite side contacting a second BE where the first and second BE are separated by a dielectric spacer. A first current is applied between the two BE, and the SHE layer generates SOT on the FL thereby switching the FL magnetization to an opposite perpendicular-to-plane direction. The SHE layer is a positive or negative SHA material, and may be a topological insulator such as BiSb. A top electrode is formed on an uppermost hard mask in each SOT device. A single etch through the FL and SHE layer ensures a reliable first current pathway that is separate from a read current pathway.

Integration scheme for three terminal spin-orbit-torque (SOT) switching devices

MTJ device performance by adding stress modulation layer to mtj device structure

Methods of critical dimension (CD) uniformity control for magnetic head devices are disclosed. In some embodiments, a method can include providing a film stack, the film stack including a substrate, a magnetoresistive (MR) sensor layer, and a hard mask layer, patterning the hard mask layer using a first mask that defines critical shape patterns other than the CD, forming a mandrel pattern using a second mask that defines the CD, and forming a sidewall spacer pattern on sidewalls of the mandrel pattern, and removing the mandrel pattern.

Method of ultra-fine critical dimension patterning for magnetic head devices

A photoresist film is patterned into an array of island shapes with improved critical dimension uniformity and no phase edges by using two alternating phase shifting masks (AltPSMs) and one post expose bake (PEB). The photoresist layer is exposed with a first AltPSM having a line/space (L/S) pattern where light through alternating clear regions on each side of an opaque line is 180&#xb0; phase shifted. Thereafter, there is a second exposure with a second AltPSM having a L/S pattern where opaque lines are aligned orthogonal to the lengthwise dimension of opaque lines in the first exposure, and with alternating 0&#xb0; and 180&#xb0; clear regions. Then, a PEB and subsequent development process are used to form an array of island shapes. The double exposure method enables smaller island shapes than conventional photolithography and uses relatively simple AltPSM designs that are easier to implement in production than other optical enhancement techniques.

Critical dimension (CD) uniformity of photoresist island patterns using alternating phase shifting mask

A method for fabricating an improved magnetic tunneling junction (MTJ) structure is described. A bottom electrode is provided on a substrate. A MTJ stack is deposited on the bottom electrode. A top electrode is deposited on the MTJ stack. A first stress modulating layer is deposited between the bottom electrode and the MTJ stack, or a second stress modulating layer is deposited between the MTJ stack and the top electrode, or both a first stress modulating layer is deposited between the bottom electrode and the MTJ stack and a second stress modulating layer is deposited between the MTJ stack and the top electrode. The top electrode and MTJ stack are patterned and etched to form a MTJ device. The stress modulating layers reduce crystal growth defects and interfacial defects during annealing and improve the interface lattice epitaxy. This will improve device performance.

A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers on a bottom electrode on a wafer is provided. A metal hard mask layer is provided on the MTJ stack. A stack of multiple dielectric hard masks is formed on the metal hard mask wherein each successive dielectric hard mask has etch selectivity with respect to its underlying and overlying layers. The dielectric hard mask layers are etched in turn selectively with respect to their underlying and overlying layers wherein each successive pattern size is smaller than the preceding pattern size. The MTJ stack is etched selectively with respect to the bottommost combination dielectric and metal hard mask pattern to form a MTJ device having a MTJ pattern size smaller than a bottommost pattern size.

Multiple hard mask patterning to fabricate 20nm and below MRAM devices

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Saratoga, CA, United States of America

Tom Zhong