Stmicroelectronics Gmbh

Other

Stmicroelectronics S.r.l.

Tom Youssef

David C McClure

Alessandro Gasparini

Rong Yin

Yamu Hu

Naren K Sahoo

Anthony Junior Casillan

David Charles Mcclure

A modulated digital input signal is passed through a conditioning circuit to generate a first input signal. An error amplifier circuit receives the first input signal and a second input signal, and controls the operation of a MOS transistor to generate an output signal that is current modulated. The output signal is sensed to generate a feedback signal. A switching circuit selectively applies the feedback signal as the second input signal in response to a transition of the modulated digital input signal from a first logic state to a second logic state. The switching circuit alternatively selectively applies a fixed reference signal as the second input signal to the error amplifier in response to a transition of the modulated digital input signal from the second logic state to the first logic state.

Current modulation circuit

An electronic timer may include a clock reference signal generator and a real time clock (RTC) circuit for generating real time data based upon the clock reference signal. The RTC circuit may include a plurality of registers each for storing a respective bit of the real time data. Further, each register may include a master latch for initially storing the real time data bit, a slave latch for subsequently storing the real time data bit, and a user latch for storing the real time data bit from the slave latch. The RTC circuit may further include a controller for causing at least some of the registers to increment based upon the clock reference signal. Additionally, the electronic timer may also advantageously include a tamper circuit for receiving a tamper event signal and causing each of the user latches to hold a time stamp therein.

Electronic device and timer therefor with tamper event time stamp features and related methods

Electronic device and timer therefor with tamper event stamp features and related methods

A power on reset circuit includes a pulse generation circuit that is connected to receive a supply voltage and respond to an initial ramp-up of that supply voltage to generate an output pulse that transitions from a low to a relatively high state tracking the supply voltage ramp-up. The pulse generation circuit further sets a feedback node in an enable state. Responsive to a flip signal received at an input node, the pulse generation circuit then transitions the output pulse from the relatively high state to the low state and sets the feedback node in a disable state. A static current control transistor switch includes a source-drain circuit coupled to the supply voltage and further includes a gate. The gate is connected to the feedback node such that the transistor switch is actuated in response to the feedback node enable state and unactuated in response to the feedback node disable state. A resistive divider circuit, including at least two resistors connected in series with each other at a tap, is connected in series with the source-drain circuit of the static current control transistor. The tap of the resistive divides circuit is connected to the input node of the pulse generation circuit to supply the flip signal.

Power on reset circuit

An integrated circuit and method for providing a switchover from the primary power source to the secondary power source to prevent a volatile element from losing stored data. The integrated circuit includes a forced power source switchover circuit for detecting that the supply level of the primary power source drops below a predefined threshold level. A switchover circuit on the integrated circuit initiates a switchover operation based upon the forced power source switchover circuit detecting that the supply level being received from the primary power source drops below the predefined threshold level. The detection by the forced power source switchover circuitry may occur on a signal level that transitions faster than a predetermined negative rate of change. The integrated circuit may be incorporated in any system having volatile elements, such as memory or a clock.

Method and circuit for switchover between a primary and a secondary power source

A circuit and method are disclosed for detecting activation of a switch, such as a mechanical switch, having a first terminal coupled to two or more voltage sources, with each voltage source providing a distinct voltage level representing a logic high level. The circuit includes first circuitry, having an output coupled to the switch for initially placing a first voltage across the switch representative of a logic low level. The circuit further includes second circuitry having an input coupled to the switch for sensing a voltage differential appearing across the switch and an output for indicating whether the voltage appearing across the switch is at any voltage representative of the logic high level, the second circuitry being controlled to selectively eliminate static current drawn by the circuit based upon the value of the output of the second circuitry.

Circuit and method for detecting the state of a switch with reduced power

A circuit and method are disclosed for detecting activation of a switch, such as a mechanical switch. The circuit may include a first circuit for temporarily driving the second terminal of the switch to a second logic level. A second circuit, coupled to the switch, senses a voltage level of the second terminal of the switch and generates an output signal representative of the voltage sensed. A sequential logic circuit is responsive to the output signal of the second circuit so as to maintain a logic value representative of the switch having been closed.

Circuit and method for detecting the state of a switch

A circuit for detecting the state of a switch having a first circuit which substantially periodically attempts to provide a voltage across the switch. A second circuit detects the state of the switch by monitoring the voltage across the switch, and responsively generates an output having a voltage level representative of the voltage appearing across the switch.

Method and circuit for detecting the state of a switch

A test mode structure and method of a multi-power-source device provides for the device to remain in a test mode, during which current draw of the device may be accurately measured, even after primary power supply to the device has been greatly reduced or completely removed. Significant reduction or removal of the primary power supply while still remaining in the test mode is necessary to counter the presence of a variable current that would otherwise be normally generated by the multi-power-source device in the test mode; the presence of the variable current during the test mode, if not negated, will not permit an accurate measurement of the current draw of the multi-power-source device. Significant reduction or removal of the primary power supply to the device would typically cause the multi-power-source device to exit the test mode and switch to a secondary supply voltage supplied by the secondary power supply, thereby foiling any attempt to measure the current draw of the device. An external control signal provided to the device ensures that the test mode remains enabled, thereby inhibiting the device from exiting the test mode and switching to the secondary power supply in a normal operating mode.

Method and structure for measurement of a multiple-power-source device during a test mode

A power supply switching circuit employs hysteresis to ensure stable, timely, and accurate transition between a primary power source and a secondary power source of an integrated circuit. A comparison element of the circuit compares a first voltage signal derived from a primary voltage of the primary power source to a second voltage signal provided by the secondary power source in order to generate a compare output signal. A voltage divider element of the circuit, characterized as having a RC constant, is coupled to the primary power source and receives the compare signal generated by the comparison element and generates the first voltage signal. A bypass element of the circuit is coupled to the voltage divider element and is controlled by the compare signal to bypass the RC constant of the voltage divider element by immediately pulling the first voltage signal to the primary voltage when, after powering up the primary power source, the first voltage signal becomes greater than the second voltage signal.

Apparatus and method for switching between two power supplies of an

A power supply switching circuit ensures stable, timely, and accurate transition between a primary power source and a secondary power source of an integrated circuit. A comparison element of the circuit compares a first voltage signal derived from a primary voltage of the primary power source to a second voltage signal, also derived from the primary voltage but having a different rate of change than the first voltage signal, to generate a compare output signal. The first and second voltage signals are characterized as being equal to each other when the primary voltage is equal to a predetermined crossover point at which the integrated circuit device will be powered by the primary voltage. When the primary voltage is less than the predetermined crossover point, a transistor element of a reference leg of a current mirror of the power supply switching circuit operates in back-bias mode and is sized large enough to ensure that the reference leg generates a large enough current to stabilize operation of the comparison element as the primary voltage ramps up until the primary voltage exceeds the predetermined crossover point.

Method and apparatus for increasing comparator gain without affecting

A low/zero power memory device includes a deselect mode of operation wherein row decoders, column decoders, write decoders, pre-coders, post-coders and like operational circuits of the memory device needed for wordline and column activation are disabled until such time as a memory device supply voltage exceeds a certain threshold. An included test mode circuit detects test mode activation and overrides application of the power fail deselect mode of operation of the device. This activates the wordline and column related operational circuits immediately at power up such that the device powers up with multiple wordlines and columns activated and ready for application of a stress test overvoltage.

Stress test mode entry at power up for low/zero power memories

An integrated circuit and associated method for switching from a power supply to a battery are provided. The integrated circuit preferably includes a memory circuit responsive to an external power supply and to a battery for storing data therein and a sleep mode latching circuit connected to the memory circuit for latching the memory circuit in a reduced power sleep mode condition so as to reduce power usage of a battery and a non-sleep mode operating condition so as to allow normal operation of the memory circuit by a power supply. The integrated circuit preferably also includes a sleep mode latch locking circuit connected to the sleep mode latching circuit and the memory circuit and responsive to a power supply for locking the sleep mode latching circuit in the non-sleep mode operating condition when power supplied from the power supply falls below a predetermined threshold so that the memory circuit is inhibited from inadvertently entering the reduced power sleep mode condition.

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Dallas, TX, United States of America

Tom Youssef