Broadcom Corporation

Avago Technologies International Sales Pte. Limited

Tom W Kwan

Sumant Ranganathan

Klaas Bult

Arya Behzad

Mehdi Hatamian

Oscar Ernesto Agazzi

Ramon Alejandro Gomez

Henry Samueli

John L Creigh

Arthur Abnous

David E Kruse

Chi-Hung Lin

Pieter Vorenkamp

Ralph A Duncan

Ning Li

Eric Bruce Blecker

Victor Chiu-Kit Fong

Chao Tang

Frank Carr

James Y C Chang

Haideh Khorramabadi

Jason A Trachewsky

Paul Anthony Lettieri

Frank Wayne Singor

Srinivasa H Garlapati

Hung-Sung Li

Xinyu Yu

Fang Lin

Christopher M Ward

Feng Su

Jeyhan Karaoguz

David A Sobel

Gregory H Efland

Ovidiu Bajdechi

Iuri Mehr

Qiang Fu

Yue Hu

Guowen Wei

John S Walley

Christopher Michael Ward

Ralph Duncan

Augustine Kuo

Monika Gupta

Greg H Efland

Michael Inerfield

Guo Wen Wei

Niug Li

Bob Lukas

Sumant Rangnathan

Frank Singor

A device including a first circuit, a second circuit, and a third circuit. The first circuit to receive a first signal and a second signal, and the first circuit to provide a third signal. The second circuit to receive a fourth signal and a fifth signal, and the second circuit to provide a sixth signal. The third circuit to receive the third signal and the sixth signal, and the third circuit to provide a seventh signal to indicate whether to track a difference between an amount of voltage provide to a driver and an amount of voltage provided by the driver or track a difference between an amount of voltage provided by a source and the amount of voltage provided to the driver.

Amplifier with output AC coupled envelope tracking supply

A circuit includes a driver to provide a voltage at a node of a load and a first circuit to facilitate determining a load current at the node. The load is a capacitive load and the first circuit facilitates determining the load current by measuring a replica current and determining a capacitance of the load using values of the voltage and the replica current.

Panel impedance sensing via driver replica current

Frequency selective analog front-end circuitry, used to convert a sensed charge signal to an analog voltage is disclosed. In one aspect, the frequency selective analog front-end circuitry includes an op-amp having an output, an inverting input and a noninverting input, a first resistor connected between the terminal of the first capacitor and the inverting input of the op-amp, a second capacitor connected between the output of the op-amp and the inverting input of the op-amp, a second resistor connected between the output of the op-amp and the inverting input of the op-amp, a third capacitor connected between the terminal of the first capacitor and the noninverting input of the op-amp, and a third resistor connected between the noninverting input of the op-amp and a reference voltage.

Frequency selective charge amplifier to attenuate common mode interferers

A CT-SDADC of the present disclosure converts the analog input signal from a representation in an analog signal domain to a representation in a digital signal domain to provide the digital output signal. The CT-SDADC achieves the analog-to-digital conversion and ELDC by switching between two phases in the SAR sub-ADC: a sampling phase and a conversion phase. During the sampling phase, the SAR sub-ADC captures the analog input signal across multiple arrays of switchable capacitors. The conversion phase comprises a number of steps, and one or more bits of the digital output signal are resolved at each step of the conversion phase. A portion of the SC-DAC is driven by the delayed CT-SDADC output during the conversion phase to effectively compensate for excess loop delay caused by the CT-SDADC feedback loop.

Method and apparatus for excess loop delay compensation in continuous-time sigma-delta analog-to-digital converters

A method and apparatus is disclosed to compensate for gate leakage currents of thin oxide devices that have very thin oxide layers in a current mirror of a digital-to-analog converter (DAC). The DAC converts a digital input signal from a digital representation in a digital signaling domain to an analog representation in an analog signaling domain to provide an analog output signal. The DAC uses one or more transistors to convert the digital input signal from the digital representation to the analog representation. These transistors are typically implemented using thin oxide devices that have very thin oxide layers and corresponding gate leakage currents that are associated with these very thin oxide layers. The current-steering DAC provides these gate leakage currents independent of its corresponding, reference source without any substantial affect upon its full scale output.

Gate leakage compensation in a current mirror

An interference tolerant capacitive touch sensor readout circuit having improved power and area efficiency is disclosed. Interference rejection for the capacitive touch sensing system is realized by transferring charge between a capacitive touch sensor and the readout circuit at frequencies outside bands where a level of interference is unacceptable. Improved power and area efficient come from the simplicity of the readout circuit which comprises a switched-capacitor integrator, a comparator, a digital accumulator and number of switches for driving a touch sensor and a capacitive feedback loop. The readout circuit is capable of interfacing with both self and mutual capacitance sensor to achieve compatibility with a larger collection of sensors and provides additional sensing and diagnostic functionalities.

Capacitive touch sensing system with interference rejection

Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.

Gigabit ethernet transceiver with analog front end

Operating a game controller to identify a user by receiving touch pad input from at least one touch sensitive pad of the game controller that has a plurality of touch sensitive elements. The touch pad input corresponds to the user's touch of at least some of the plurality of touch sensitive elements. The touch pad input is at least partially processed by processing circuitry of the game controller and transmitted to a game console via a communications interface of the game controller for processing of the at least partially processed touch pad input to identify the user via pattern recognition. At least partially processing the touch pad input can be by identifying at least one finger orientation, at least one finger spacing, at least one finger width, a plurality of finger knuckle/joint locations, and/or a plurality of finger lengths based upon the touch pad input.

Hand-held gaming device that identifies user based upon input from touch sensitive panel

Operating a remote control to identify a user by receiving touch pad input from at least one touch sensitive element of the remote control that has a plurality of touch sensitive elements. The touch pad input corresponds to the user's touch of at least some of the plurality of touch sensitive elements. The touch pad input is at least partially processed by processing circuitry of the remote control and transmitted to a multimedia system console via a communications interface of the remote control for processing of the at least partially processed touch pad input to identify the user via pattern recognition. At least partially processing the touch pad input can be by identifying at least one finger orientation, at least one finger spacing, at least one finger width, a plurality of finger knuckle/joint locations, and/or a plurality of finger lengths based upon the touch pad input.

Remote control for multimedia system having touch sensitive panel for user ID

The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.

Scalable integrated circuit high density capacitors

A method and apparatus is disclosed to compensate for gate leakage currents of thin oxide devices that have very thin oxide layers in a current mirror of a digital-to-analog converter (DAC). The DAC converts a digital input signal from a digital representation in a digital signaling domain to an analog representation in an analog signaling domain to provide an analog output signal. The DAC uses one or more transistors to convert the digital input signal from the digital representation to the analog representation. These transistors are typically implemented using thin oxide devices that have very thin oxide layers and corresponding gate leakage currents that are associated with these very thin oxide layers. The current-steering DAC provides these gate leakage currents independent of its corresponding reference source without any substantial affect upon its full scale output.

A second output transmission signal ('TX') added to a line driver is a scaled version of the main output transmission signal ('TX'). TXis scaled from TXby a variable scale factor K. An adaptive hybrid circuit subtracts TXand TXfrom a line signal carrying both a line transmission signal and a line received signal (&#x201c;RX&#x201d;). A programmable impedance Zis coupled between the TXoutput of the line driver and the RX output of the adaptive hybrid circuit. A transmission echo in the output RX signal is measured. K and Zare then adaptively tuned to minimize the transmission echo. The hybrid in this case becomes a 4-port network, one port specifically added to adaptively cancel the transmission echo in the RX output of the adaptive hybrid circuit. Alternatively, the hybrid may be a 3-port hybrid including variable impedances to cancel the line transmission signal.

Line driver for an adaptive hybrid circuit

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.

Fully integrated tuner architecture

A frequency-locked clock generator includes a voltage-controlled oscillator (VCO), a frequency-to-current converter, a reference current source and a gain stage. The VCO generates an output signal. The frequency-to-current converter generates a converter current proportional to a frequency of the output signal. The reference current source generates a reference current. The gain stage generates a control signal based on a difference between the converter current and the reference current. The control signal is applied to the VCO to adjust the frequency of the output signal. Feedback forces the VCO to generate an output clock signal such that the corresponding current it produces (i.e., the converter current) is equal to the reference current. When in lock, the frequency of the output signal is determined by a time constant (or equivalent time constant) of the frequency-locked clock generator.

Frequency-locked clock generator

The present invention relates generally to analog-to-digital converters (ADCs). Embodiments of the present invention provide novel ADC architectures directed at reducing the overall ADC area and power consumption. Embodiments of the present invention may be used in pipelined ADCs, cyclic ADCs, and successive approximation (SAR) ADCs, for example. Further, embodiments of the present invention may be implemented using both single-ended and differential configurations.

Area-efficient analog-to-digital converter

Growing community of inventors

Cupertino, CA, United States of America

Tom W Kwan