Wang Laboratories, Inc.

Symetrix Corporation

Tom R Kibler

David L Whipple

James B MacDonald

Stephen W Olson

Kevin T Mahoney

Robert R Trottier

Peter A Morrison

Robert C Nash

Daniel R Ries

George B Bennett

Andrew N Fu

Nils O Edstrom

Bhikoo J Patel

John P Long

John B Neal

Ronald V Simmons

Stewart A Davis

Scheduling software provides date and time allocation of resources to a sequence of processes for manufacturing a desired item. Scheduling is performed by a backward-forward method and alternatively by an backward-jump forward method to meet a requested due date. Resources are dynamically allocated to satisfy processes according to pre-established rules for allocation. Also resources are allocated in certain amounts or in a predetermined pattern to minimize waste or left over amounts of the resource. To allocate certain resources, purchase or production of the resource is scheduled first.

Scheduling method and apparatus

An I/O structure for use in a digital data processing system of the type in which system components including a processor and a system memory are connected by a system bus. The I/O structure includes a system bus interface connected to the system bus, a synchronous satellite processing unit (SPU) bus connected to the system bus interface, one or more satellite processing units (SPUs) connected to the SPU bus, and peripheral devices attached to the satellite processing units. Each SPU has three main components: control logic including a microprocessor for controlling the SPU, a device adapter specific to the peripheral device for controlling the peripheral device and transferring data between the peripheral device and the SPU, and an interface unit connected to the control logic and the device adapter for providing I/O communications to the SPU bus and responding to I/O communications on the SPU bus. The I/O communications fall into two classes: communications to SPUs and communications to system components. The communications to SPUs all require a single SPU bus cycle; the communications to system components require one or more cycles. The system bus interface translates communications to system components into communications on the system bus and translates communications on the system bus intended for a SPU into communications to SPUs. The SPU bus includes first lines for carrying an I/O command and an identifier for an SPU involved in the communication and second lines for carrying the contents of the communication. In multicycle communications, the I/O command and identifier remain on the first lines for all cycles, but the information on the second lines varies from cycle to cycle.

I/O structure for information processing system

Growing community of inventors

Groton, MA, United States of America

Tom R Kibler