International Business Machines Corporation

Synopsys, Inc.

Amazon Technologies, Inc.

Tom Kolan

Vitali Sokhin

Hillel Mendelson

Shay Aviv

Gil Eliezer Shurek

Shiri Moran

Adi Habusha

Dean G Bair

Anatoly Koyfman

Ronny Morad

Shai Doron

Elena Tsanko

Wesam Saleem Ibraheem

Hernan Theiler

Eliran Roffe

Idan Horowitz

Nicolas Worms

Hagai Hadad

Alex Lvovsky

Ilan Wachtel

Hardware errors can be detected by generating a plurality of test templates to perform testing on an integrated circuit (IC) device. A set of random tests can be generated corresponding to the plurality of test templates. The set of random tests can be executed on the IC device for multiple passes, and the results of the multiple passes can be compared to detect the hardware error in the IC device. The set of random tests can be generated as a binary image for execution on the IC device. The IC device may include multiple processing cores, and executing the multiple passes may include changing logical role of each processing core between subsequent passes. The set of random tests can be executed in a bare-metal mode, or at an application level of the IC device.

Detecting hardware errors

A computer-implemented method including: providing a test template for a hardware system-under-test comprising one or more execution threads, wherein the test template comprises a branching instruction to a predetermined shared memory address accessible by at least some of the one or more execution threads; generating and storing, at the predetermined shared memory address, a sequence of instructions which conform to the test template; building, based, at least in part, on the test template, an executable image of a hardware exerciser, wherein the hardware exerciser is adapted to control a test cycle of the hardware system-under-test, and wherein the test cycle comprises at least generation and execution of a test; and executing the executable image of the hardware exerciser by at least a first execution thread of the one or more execution threads of the hardware system-under-test.

Random instruction-side stressing in post-silicon validation

A method for performing an address translation context switch includes initializing a computer processor to a first context by storing information identifying the first context in a control register of the computer processor. The first context specifies a mapping of virtual addresses of instructions to physical memory addresses in a first memory area. Information identifying a second context is stored in a memory address translation independent storage, where the second context specifies mapping of virtual addresses of instructions to physical memory addresses in a second memory area. The information identifying the second context is written to the control register of the computer processor.

Validating address space context switches by loading an alternative address space from an address translation independent location

A system, program product, and method for validating a system under test (SUT). The method includes generating one or more application programming interface (API) requests. The method also includes selecting one or more random biases for one or more properties of the one or more API requests. The method further includes generating a random sample of one or more values from an input domain space, wherein the one or more values are associated with one or more respective fields of the API being requested.

Test space sampling for model-based biased random system test through rest API

An example system includes a processor that can receive a queue testing package. The processor can divide a hardware (HW) queue system to be tested into different types of queues. The processor can also generate a test using the different types of queues. The processor can further execute multiple instances of the generated test. The processor can also further compare results of the multiple instances of the test to detect a hardware fault in the hardware queue system.

Testing of hardware queue systems using on device test generation

Embodiments relate to a system, program product, and method for integrating compiler-based testing in post-silicon validation. The method includes generating a test program through a device-under-test (DUT). The method also includes generating a plurality of memory intervals and injecting the plurality of memory intervals into the test program. The method further includes injecting a plurality of compiled test snippets into the test program and executing one or more post-silicon validation tests for the DUT with the test program.

Compiler-based code generation for post-silicon validation

Embodiments relate to a system, program product, and method for validating a system under test (SUT). The method includes selecting one or more random biases for one or more properties of the one or more API requests. The method also includes transmitting the one or more API requests to the SUT, transmitting an API response from the SUT for each of the one or more API requests, and validating each API response.

Model-based biased random system test through rest API

A method, apparatus and product for utilizing address translation structures for testing address translation cache. The method comprises: obtaining a first address translation structure that comprises multiple levels, including a first top level which connects a sub-structure of the first address translation structure using pointers thereto; determining, based on the first address translation structure, a second address translation structure, wherein the second address translation structure comprises a second top level that is determined based on the first top level, wherein the second top level connects the sub-structure of the first address translation structure; executing a test so as to verify operation of an address translation cache of a target processor at least by: adding a plurality of cache lines to the address translation cache, wherein said adding is based on the address translation structures; and verifying the operation of the address translation cache using one or more memory access operations.

Testing address translation cache

Embodiments relate to a system, program product, and method for random generation of recoverable errors in the generated instruction stream for post-silicon validation testing. The intentional raising and handling of exceptions in post-silicon validation exercisers randomly creates recoverable errors in a generated instruction test stream. Multiple exceptions may be raised either in a single instruction or in multiple instructions, while the present instruction is permitted to fully execute. The errors responsible for raising the exceptions are automatically repaired.

Recoverable exceptions generation and handling for post-silicon validation

A method for testing an integrated circuit, comprising: accessing a database associated with a test template, wherein said test template is configured to test a selected function of the integrated circuit; storing, in said database, data corresponding to at least partial predicted results of one or more random instruction sequences generated based on said test template; generating, by an automated test generation tool, a random instruction sequence based on said test template; executing said instruction sequence by a hardware exerciser, in the integrated circuit; and comparing results of said instruction sequence with said at least partial predicted results, to verify a function of said integrated circuit.

Partial-results post-silicon hardware exerciser

A method, apparatus and a product for utilizing translation tables for testing processors. The method is used for testing a target processor that utilizes different translation tables to translate virtual addresses to physical addresses. The method comprises obtaining a test template that comprises directives to be executed in different contexts, during each of which a different translation table is utilized to translate virtual addresses to physical addresses. The translation tables to be used by the target processor in the different contexts are determined, so that the translation tables overlap, at least in part.

Utilizing translation tables for testing processors

Method, apparatus and product for automatically introducing register dependency into tests. A test template represents an abstract test scenario to be utilized for testing a target processor. The abstract test scenario requires that a value be assigned to a register. A test that implements the abstract test scenario is generated. The test is a set of instructions that are executable by the target processor. The generation of the test comprises: determining a memory address to retain the value in a memory that is accessible to the target processor; and adding to the test an instruction to load to the register the value from the memory address, whereby adding a register dependency to the test that is not required by the abstract test scenario. The test can be executed on the target processor or simulation thereof.

Automatically introducing register dependencies to tests

A method, system and computer program product, the method comprising: obtaining a test template comprising a multiplicity of elements, including a first element and another element; generating a partially instantiated test template comprising a first instance for the first element and the another element in an uninstantiated form; generating, based on the partially instantiated test template, a first test complying with the test template, the first test comprising the first instance for the first element and an instance for the another element; executing the first test to obtain a first result; generating, based on the partially instantiated test template, a second test complying with the test template, the second test comprising the first instance for the first element and another instance for the another element, thereby using the first instance for generating the first and second tests; and executing the second test to obtain a second result.

Method and apparatus for test generation

Techniques for modifying a circuit are described herein. In some examples, a method includes generating a set of testing data and detecting a predetermined modification to a translation path corresponding to a memory address mapping, the predetermined modification to change a physical memory address of the testing data associated with a virtual memory address to a second physical memory address of the testing data. The method can also include generating a test template comprising a first instruction to implement the predetermined modification and a second instruction comprising the second physical memory address in the translation path and transmitting the test template to the circuit for each of a plurality of software instruction threads. Furthermore, the method can include detecting a defect in the execution of the test template by the circuit and modifying the circuit to prevent the defect during execution of the test template.

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Haifa, Israel

Tom Kolan