Applied Materials, Inc.

Varian Semiconductor Equipment Associates, Inc.

Tom Ho Wing Yu

Nobuyuki Sasaki

Rongjun Wang

Tza-Jing Gung

Kai Wu

Jianxin Lei

Xi Cen

Wenting Hou

Feihu Wang

Chunming Zhou

Peiqi Wang

Wei Min Chan

Ju Ik Kang

Min Heon

Adolph Miller Allen

Zhong Qiang Hua

Rajesh Prasad

Kyu-Ha Shim

Tzu-Yu Liu

Viabhav Soni

Ravi Rajagopalan

Method for forming tungsten gap fill on a structure, including high aspect ratio structures includes depositing a tungsten liner in the structure using a physical vapor deposition (PVD) process with high ionization and an ambient gas of argon or krypton. The PVD process is performed at a temperature of approximately 20 degrees Celsius to approximately 300 degrees Celsius. The method further includes treating the structure with a nitridation process and depositing bulk fill tungsten into the structure using a chemical vapor deposition (CVD) process to form a seam suppressed boron free tungsten fill. The CVD process is performed at a temperature of approximately 300 degrees Celsius to approximately 500 degrees Celsius and at a pressure of approximately 5 Torr to approximately 300 Torr.

Methods for low resistivity and stress tungsten gap fill

Methods and apparatus for low resistivity and stress tungsten gap fill

Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.

Silicon-containing layer for bit line resistance reduction

A method may include depositing a carbon layer on a substrate using physical vapor deposition, wherein the carbon layer exhibits compressive stress, and is characterized by a first stress value; and directing a dose of low-mass species into the carbon layer, wherein, after the directing, the carbon layer exhibits a second stress value, less compressive than the first stress value.

Techniques for forming low stress etch-resistant mask using implantation

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Campbell, CA, United States of America

Tom Ho Wing Yu