Intel Corporation

Tom A Piazza

Aditya Sreenivas

Val Gene Cook

Alankar Saxena

Brian D Rauchfuss

Krishnan Sreenivas

Embodiments of the present invention provide a method and apparatus for optimally mapping a tiled memory surface to two memory channels, operating in an interleaved fashion, maximizing the memory efficiency of the two channels, while maintaining the desired access granularity. In particular, an incoming request address is used to generate memory addresses for memory channels based on tile and request parameters. The memory controller stores the set of tiled data in the memory in a format such that selected sets of tiled data are stored in alternating channels of memory, such that data blocks are accessible at the same time, as opposed to sequentially. Thus if the memory controller received a block of data from a source, such as a graphics engine, the memory controller would store portions of the block of data within a single tile in the memory, partitioned such that it is retrievable via alternate channels of memory at the same time.

Dual memory channel interleaving for graphics and video

An anisotropic filtering technique includes defining pixel elements in two dimensions and defining at least one object having three dimensional surfaces in a three-dimensional model space and storing texel elements in two dimensions defining a texture map bearing a relationship to the three dimensional surfaces of the at least one object. Each pixel element to be texture mapped is divided into a group of sub-pixel elements and the sub-pixel elements are separately texture mapped. The resultant textures of the sub-pixel elements are averaged to obtain a texture for their respective pixel element.

Anisotropic filtering technique

In one embodiment, the invention is a method. The method includes monitoring a data stream. The method also includes partitioning a cache into two sub-caches based on monitoring the data stream.

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Granite Bay, CA, United States of America

Tom A Piazza