Lam Research Corporation

Tom A Kamp

John Stephen Drewery

Alex Paterson

John Edward Daugherty

Yoshie Kimura

Ming-Kuei Tseng

Haoquan Yan

Ali Sucipto Tan

Bruce Edmund Freeman

Keith William Gaff

Arthur H Sato

Eric A Pape

Gowri Kamarthy

Neema Rastgar

Rohit Deshpande

Carlos Leal-Verdugo

Michael Carl Drymon

Eric A Hudson

Qian Fu

Reza Arghavani

Mirzafer K Abatchev

Samantha SiamHwa Tan

Alexander Miller Paterson

Richard Alan Gottscho

Vahid Vahedi

Saravanapriyan Sriraman

Gerardo Delgadino

Shashank C Deshmukh

Vijayakumar C Venugopal

Alan Jeffrey Miller

Aaron Eppler

Shenjian Liu

Yoko Yamaguchi

Xiang Zhou

Chen Xu

Linda B Braly

Chris Lee

Duming Zhang

I C Jang

Steve Lee

Rodolfo P Belen, Jr

A method for adjusting a height of an edge ring arranged around an outer portion of a substrate support includes receiving at least one input indicative of one or more erosion rates of the edge ring. The at least one input includes a plurality of erosion rates for respective usage periods of a substrate processing system. The method further includes determining at least one erosion rate of the edge ring using the plurality of erosion rates for the respective usage periods, monitoring an overall usage of the edge ring and storing the overall usage of the edge ring in a memory, calculating an amount of erosion of the edge ring based on the determined at least one erosion rate and the overall usage of the edge ring, and adjusting the height of the edge ring based on the calculated amount of erosion to compensate for the calculated amount of erosion.

System, method, and user interface for edge ring wear compensation

A processing chamber such as a plasma etch chamber can perform deposition and etch operations, where byproducts of the deposition and etch operations can build up in a vacuum pump system fluidly coupled to the processing chamber. A vacuum pump system may have multiple roughing pumps so that etch gases can be diverted a roughing pump and deposition precursors can be diverted to another roughing pump. A divert line may route unused deposition precursors through a separate roughing pump. Deposition byproducts can be prevented from forming by incorporating one or more gas ejectors or venturi pumps at an outlet of a primary pump in a vacuum pump system. Cleaning operations, such as waferless automated cleaning operations, using certain clean chemistries may remove deposition byproducts before or after etch operations.

Vacuum pump protection against deposition byproduct buildup

A controller for adjusting a height of an edge ring in a substrate processing system includes an edge ring wear calculation module configured to receive at least one input indicative of one or more erosion rates of the edge ring, calculate at least one erosion rate of the edge ring based on the at least one input, and calculate an amount of erosion of the edge ring based on the at least one erosion rate. An actuator control module is configured to adjust the height of the edge ring based on the amount of erosion as calculated by the edge ring wear calculation module.

System and method for edge ring wear compensation

A method for etching a substrate includes performing, in a plasma chamber, a first etch of a substrate material using a plasma etch process. The first etch forms features to a first depth in the material. Following the first etch, the method includes performing, in the plasma chamber without removing the substrate from the chamber, an atomic layer passivation (ALP) process to deposit a conformal film of passivation over the mask and the features formed during the first etch. The ALP process uses a vapor from a liquid precursor to form passivation over the features and the mask. The method further includes performing, in the plasma chamber, a second etch of the material using the plasma etch process. The conformal film of passivation is configured to protect the mask and sidewalls of the features during the second etch. A plasma processing system also is described.

Integrated atomic layer passivation in TCP etch chamber and in-situ etch-ALP method

Methods of and apparatuses for laterally etching semiconductor substrates using an atomic layer etch process involving exposing an oxidized surface of a semiconductor substrate to a fluorine-containing etch gas and heating the substrate to remove non-volatile etch byproducts by a sublimation mechanism are provided herein. Methods also including additionally pulsing a hydrogen-containing gas when pulsing the fluorine-containing etch gas. Apparatuses also include an ammonia mixing manifold suitable for separately preparing and mixing ammonia for use in various tools.

Self limiting lateral atomic layer etch

A method for processing a stack with a carbon based patterned mask is provided. The stack is placed in an etch chamber. A silicon oxide layer is deposited by atomic layer deposition over the carbon based patterned mask by providing a plurality of cycles, wherein each of the cycles of the plurality of cycles, comprises providing a silicon precursor deposition phase, comprising flowing an atomic layer deposition precursor gas into the etch chamber, where the atomic layer deposition precursor gas is deposited while plasmaless and stopping the flow of the atomic layer deposition precursor gas and providing an oxygen deposition phase, comprising flowing ozone gas into the etch chamber, wherein the ozone gas binds with the deposited precursor gas while plasmaless and stopping the flow of ozone gas into the etch chamber. Part of the silicon oxide layer is etched. The stack is removed from the etch chamber.

Silicon-based deposition for semiconductor processing

A gas plenum arrangement for a substrate processing system includes a gas plenum body arranged to define a gas plenum between a coil and a processing chamber. The coil is arranged outside of an outer edge of the gas plenum body. A plurality of flux attenuating portions is arranged outside of the outer edge of the gas plenum body. The flux attenuation portions overlap the coil.

Gas plenum arrangement for improving etch non-uniformity in transformer-coupled plasma systems

An edge ring assembly for a plasma processing chamber is provided, including: an edge ring configured to surround an electrostatic chuck (ESC) that is configured for electrical connection to a first RF power supply, the ESC having a top surface for supporting a substrate and an annular step surrounding the top surface, the annular step defining an annular shelf that is lower than the top surface; an annular electrode disposed below the edge ring in the annular step and above the annular shelf; a dielectric ring disposed below the annular electrode for isolating the annular electrode from the ESC, the dielectric ring positioned in the annular step over the annular shelf; and, a plurality of insulated connectors disposed through the ESC and through the dielectric ring, each of the plurality of insulated connectors providing electrical connection between a second RF power supply and the annular electrode.

Extreme edge sheath and wafer profile tuning through edge-localized ion trajectory control and plasma operation

A method for etching an etch layer in a stack over a substrate wherein the etch layer is under a mask layer which is under a patterned organic mask is provided. The stack and substrate is placed on a support in the plasma chamber. A silicon based layer is deposited in situ over the stack. The silicon based layer is etched to form silicon based sidewalls or spacers on sides of the patterned organic mask. The mask layer is selectively etched with respect to the silicon based sidewalls or spacers, wherein the selectively etching the mask layer undercuts the silicon based sidewalls or spacers. The etch layer is selectively etched with respect to the mask layer. The stack and substrate are removed from the support and the plasma chamber.

Shadow trim line edge roughness reduction

A substrate processing system includes a processing chamber including a dielectric window and a pedestal for supporting a substrate during processing. A gas supply system supplies gas to the processing chamber. A coil is arranged outside of the processing chamber adjacent to the dielectric window. A radio frequency (RF) source supplies RF signals to the coil to create RF plasma in the processing chamber. N flux attenuating portions are arranged in a spaced pattern adjacent the coil, wherein N is an integer greater than one.

Systems and methods for improving wafer etch non-uniformity when using transformer-coupled plasma

The embodiments herein relate to methods and apparatus for etching a recessed feature in dielectric material. In various embodiments, a recessed feature is formed in two etching operations. The first etching operation partially etches the features and may take place in a reactor configured to produce a capacitively coupled plasma. The first etching operation may end before the underlying semiconductor material experiences substantial damage due to penetration of ions through the dielectric atop the semiconductor material. The second etching operation may take place in a reactor configured to produce an inductively coupled plasma. Both the first and second etching operations may themselves be multi-step, cyclic processes.

Integrated etch/clean for dielectric etch applications

Exemplary embodiments are directed to controlling CD uniformity of a wafer by controlling trim time on temperature in a plasma processing system. The plasma processing system has a wafer support assembly including a plurality of independently controllable temperature control zones across a chuck and a controller that controls each temperature control zone. The controller receives process control and temperature data associated with at least one wafer previously processed in a plasma chamber of the plasma processing system. The controller also receives critical device parameters of a current wafer to be processed in the plasma chamber. The controller calculates a target trim time and a target temperature profile of the current wafer based on the process control and temperature data of the at least one previously processed wafers and the critical device parameters of the current wafer. The current wafer as subjected to a trimming operation for a duration of the target trim time while controlling temperatures in the temperature control zones to thereby control temperature of each device die location based on the target temperature profile.

Controlling CD and CD uniformity with trim time and temperature on a wafer by wafer basis

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San Jose, CA, United States of America

Tom A Kamp