Other

Honeywell G.m.b.h.

Tom A Agan

Alexander Mikhailovich Shukh

A magnetic memory device that comprises a substrate, a memory cell including a magnetic tunnel junction which comprises a free ferromagnetic layer having a reversible magnetization direction directed perpendicular to the substrate, a pinned ferromagnetic layer having a fixed magnetization direction directed perpendicular to the substrate, and an insulating tunnel barrier layer disposed between the pinned and free layers, a first electrical circuit for applying a first current to a first conductor electrically coupled to the free layer to produce a bias magnetic field along a hard axis of the free layer, a second electrical circuit for applying a second current to a second conductor electrically coupled to the pinned layer to cause a spin momentum transfer in the free layer, wherein magnitudes of the bias magnetic field and spin momentum transfer in combination exceed a threshold and thus reverse the magnetization direction of the free layer.

High density magnetic random access memory

One embodiment of a magnetic memory device comprises a substrate and a plurality of planar memory arrays stacked on the substrate, each memory array includes a plurality of parallel first conductive lines, each first conductive line includes a ferromagnetic cladding, a plurality of parallel second conductive lines overlapping the first conductive lines at a plurality of intersection regions, a plurality of magnetic tunnel junctions, each magnetic tunnel junction has a controllable electrical resistance, is disposed at an intersection region and electrically coupled to one of the first conductive lines at its first end and to one of the second conductive lines at its second end. The electrical resistance of the magnetic tunnel junction is controlled by a joint effect of a spin-polarized current running between the first and second ends and a bias magnetic field applied simultaneously to said each magnetic tunnel junction. Other embodiments are described and shown.

A nonvolatile latch circuit that includes a logic circuitry comprising at least an input terminal, a clock terminal, an output terminal, and a nonvolatile memory element. The logic circuitry is electrically coupled to a high voltage source at a first source terminal and to a low voltage source at a second source terminal. The nonvolatile memory element is electrically coupled to the output terminal at a first end and to a intermediate voltage source at a second end. A logic state of the latch circuit responds to an input signal during an active period of a clock signal. A logic state of the nonvolatile memory element is controlled by a bidirectional current running between the first and second ends. An electrical potential of the intermediate voltage source is higher than that of the low voltage source but lower than that of the high voltage source.

Nonvolatile latch circuit

A nonvolatile full adder circuit comprising a full adder electrical circuitry comprising three input terminals for receiving two input and carry-in signals, a sum output terminal, and an carry-out output terminal; first and second nonvolatile memory elements electrically coupled to the first and second output terminal, respectively at their first ends and to an intermediate voltage source at their second ends. The nonvolatile memory elements comprise two stable logic states. A logic state each of the of the nonvolatile memory elements is controlled by a bidirectional electrical current running between its first and second ends. The full adder circuitry is electrically coupled to a high voltage source at its first source terminal and to a low voltage source at its second source terminal, wherein an electrical potential of the intermediate voltage source is lower than that of the high voltage source but higher than that of the low voltage source.

Nonvolatile full adder circuit

Full duplex CMOS communication is accomplished over a single electrical interconnect by transmitting a signal in one direction using standard voltages indicative of CMOS logic levels, and by measuring the current needed to maintain these voltages to determine the signal transmitted in the opposite direction.

Full duplex CMOS communication

A test circuit for input threshold voltage of an integrated circuit uses input pins and logic elements connected in a tree arrangement. The output of the tree controls programmable resistors to indicate pull-up or pull-down. The test circuit eliminates the need for a dedicated output pin for the testing formation.

Parametric test circuit

Logic level shifter for coupling a first logic circuit having a first voltage level power supply to a second logic circuit with the shifter and the second logic circuit having a second voltage level power supply and with the second voltage level supply applied at a time when the first level voltage supply is not applied. The level shifter maintains its outputs at either a reference ground voltage or the second level voltage when the second level voltage supply is present and the first level voltage supply is not present.

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Maple Grove, MN, United States of America

Tom A Agan