Microsoft Technology Licensing, LLC

Tolga Ozguner

Miguel Comparan

Jeffrey Powers Bradford

Ryan Scott Haraden

Gene Leung

Adam James Muff

Christopher Jon Johnson

Ishan Jitendra Bhatt

Robert Allen Shearer

Jonathan Kent Ross

Elene Terry

Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power. The systems and methods can also be adapted to work with compressed image data and multiple LSR processing engines.

No miss cache structure for real-time image transformations with multiple LSR processing engines

Optimizations are provided for late stage reprojection processing for a multi-layered scene. A multi-layered scene is generated. Late stage reprojection processing is applied to a first layer and different late stage reprojection processing is applied to a second layer. The late stage reprojection processing that is applied to the second layer includes one or more transformations that are applied to the second layer. After the late stage reprojection processing on the various layers is complete, a unified layer is created by compositing the layers together. Then, the render the unified layer is rendered.

Selectively applying reprojection processing to multi-layer scenes for optimizing late stage reprojection power

Optimizations are provided for late stage reprojection processing for a multi-layered scene. A scene is generated, which is based on a predicted pose of a portion of a computer system. A sub-region is identified within one of the layers and is isolated from the other regions in the scene. Thereafter, late stage reprojection processing is applied to that sub-region selectively/differently than other regions in the scene that do not undergo the same late state reprojection processing.

Selective application of reprojection processing on layer sub-regions for optimizing late stage reprojection power

Systems and methods for multistage post-rendering image transformation are provided. The system may include a transform generation module arranged to dynamically generate an image transformation. The system may include a transform data generation module arranged to generate first and second transformation data by applying the generated image transformation for first and second sampling positions and storing the transformation data in a memory. The system may include a first image transformation stage that selects the first and second transformation data for a destination image position and calculates an estimated source image position based on the selected first and second transformation data. The system may include a second image transformation stage that selects the first and second transformation data for the destination image position, retrieves the first and second transformation data from the memory, and recalculates an estimated source image position based on the selected first and second transformation data.

Methods and systems for multistage post-rendering image transformation

Techniques for post-rendering image transformation including outputting an image frame including a plurality of first pixels by sequentially generating and outputting multiple color component fields including a first color component field and a second color component field by applying one or more two-dimensional (2D) image transformations to at least one portion of the plurality of source pixels by first, second, and third image transformation pipelines, to generate transformed pixel color data for the first color component field and the second color component field.

Post-rendering image transformation using parallel image transformation pipelines

Techniques for controlling access to a memory are provided. The techniques may include receiving and storing output pixel data in a buffer, providing the stored output pixel data to a display controller, receiving stored output pixel data from the buffer at the display controller, switching to a second operating mode state based at least on an amount of available data in the buffer being less than or equal to a threshold, identifying a portion of the image data stored in a memory device for use in generating output pixel data for an updated image, and, in response to operating in the second operating mode, generating the output pixel data without issuing a memory read command via an interconnect to retrieve the portion of the initial image while operating in the second operating mode, and providing the output pixel data to the buffer.

Reducing negative effects of insufficient data throughput for real-time processing

Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power.

No miss cache structure for real-time image transformations

Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power. The systems and methods can also be adapted to work with compressed image data.

No miss cache structure for real-time image transformations with data compression

Systems and methods for controlling access to a memory are provided. The system may include a buffer to store output data generated by a processing module, and provide the output data to a real-time module, and a buffer monitoring circuit to output an underflow approaching state indication in response to an amount of available data in the buffer being less than or equal to a threshold. The system may include a memory access module arranged to receive memory requests issued by the processing module, and configured to, while operating in a first mode, respond to memory requests with corresponding data retrieved from the memory, switch to operating in a second mode in response to receiving the underflow approaching state indication, and in response to operating in the second mode, respond to memory requests indicating the memory access module did not attempt to retrieve corresponding data from the memory.

An interrupt controller includes a fabric slave that can receive MMIO operation requests, a plurality of output interrupt lines, a plurality of interrupt registers with each interrupt register corresponding to an output interrupt line, a MMIO routing circuit in communication with the fabric slave and the interrupt registers, a plurality of input interrupt lines for receiving line interrupts, and a line interrupt routing circuit in communication with the input interrupt lines and the interrupt registers. The interrupt registers store data for an interrupt that serves as an indication of the source of the interrupt and/or what task(s) need to be done for the interrupt.

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Redmond, WA, United States of America

Tolga Ozguner