Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Renesas Electronics Corporation

Tokuya Osawa

Hideshi Maeno

Masaru Haraguchi

Yoshikazu Morooka

Chikayoshi Morishima

Hiroshi Kinoshita

Yoshihiro Yamashita

A semiconductor device in the present invention includes a DLL circuit which determines a phase shift amount, an arithmetic circuit which shifts the phase shift amount by a predetermined phase at test mode time, registers which set the phase shift amount, and a transmission circuit which shifts a phase to the set phase to transmit or receive a signal. The transmission circuit has a first phase shifter which shifts a first signal to the set phase, a first bidirectional buffer which loops back the first signal at the test mode time, a second phase shifter which phase-shifts the signal outputted from the first bidirectional buffer, a third phase shifter which phase-shifts a third signal, a second bidirectional buffer which loops back the third signal at the test mode time, a fourth phase shifter which phase-shifts the signal outputted from the second bidirectional buffer, and a FIFO which takes out an output signal of the second phase shifter or the fourth phase shifter.

Semiconductor device which transmits or receives a signal to or from an external memory by a DDR system

A variable delay line receives and delays a data strobe signal transferred from a data source side in synchronization with a transfer data by a predetermined period, and produces a delayed data strobe signal and the non-delayed data strobe signal to a detector. The detector determines that a preamble period ends and effective data is transferred, when the delayed data strobe signal is at the L level at the time of rising of the non-delayed data strobe signal from the L level to the H level. According to a result of detection, an interface circuit unit takes in the transfer data and initializes a take-in address. The data strobe signal changes to a high-impedance state when a postamble ends. An influence of a glitch noise is avoided upon this change of the data strobe signal, and the data transfer can be executed fast and accurately.

Interface circuit

There is provided a semiconductor device including an output buffer circuit which reduces an area occupied by a circuit for impedance adjustment and allows high-speed impedance adjustment. In an impedance measuring circuit, the impedance values of reference transistors having the same sizes as those of a plurality of transistors composing the output buffer circuit which are equal in size are measured. An impedance code generating circuit outputs impedance codes corresponding to the impedance values of the reference transistors to an output buffer code generating circuit based on the result of the measurement from the impedance measuring circuit. The output buffer code generating circuit generates output buffer codes for adjusting the impedance of the output buffer circuit by performing an arithmetic operation process to provide an objective impedance based on the impedance codes.

Semiconductor device and impedance adjusting method thereof

An apparatus for testing a semiconductor integrated circuit using an actual operating frequency of the semiconductor integrated circuit includes a test target circuit which is to be tested and has a scan path in the test target circuit for executing a test. The apparatus also includes a test pattern generation circuit which generates, after completion of the test, a signal for scanning out a test result synchronously with an edge of a test clock signal with a lower frequency than the actual operating frequency, and outputs a scan-out control signal to the scan path.

Apparatus for testing semiconductor integrated circuits

A semiconductor integrated circuit device with fault analysis function performs test operation for a memory circuit (such as a RAM) in which a comparison control circuit ( ) generates a comparison control signal CCMP in order to select one or more memory cells in each memory cell group ( and ) corresponding to a single bit, a specified row, a specified bit, or a specified pattern, and then outputs the comparison control signal CCMP to scan flip flops ( and ) each including a comparator ( ). The comparator ( ) performs the comparison operation between data and expected values EXP and then outputs a comparison result only when address signals are input and data are red from memory cells, as the object of test, addressed by these address signals.

Semiconductor integrated circuit device with fault analysis function

A semiconductor integrated circuit device includes a memory circuit and a flag generator. The memory circuit is a circuit with a test circuit and includes a redundant circuit. The flag generator loads compared result information serially output from the memory circuit, and outputs flag signals if the compared result information includes at least one piece of mismatch information. This makes it possible to solve a problem of a conventional semiconductor integrated circuit device in that it takes a long time for carrying out a fault test of bits constituting the memory circuit.

Semiconductor integrated circuit device with test circuit

In a normal operation, a shift mode signal (SM) is set to '0' to propagate signals applied to '0'-input ends of selectors (10 to 12), i.e., outputs of a logic unit (80). In a logic scan test on logic units (80, 81), by setting a test-mode signal to '1', an ordinary scan test is performed with a scan path of simple configuration, having bits as much as write data and employing scan flip flops consisting of pairs of selectors (10 to 12) and flip flops (30 to 32) respectively. The flip flops used for writing in the normal operation can be also used as those used for the scan flip flops in the logic test. Thus, a configuration of the scan path to achieve excellent area-efficiency is provided.

Test circuit

In a small-size device, one input terminals of a plurality of AND circuits are connected in series. The other terminals of the plurality of AND circuits receive failure information held by a register circuit. Among the AND circuits, by changing values at the AND circuits which are connected in an output direction (i.e., most significant bit side) of an AND circuit receiving a failure bit and values at the AND circuits which are connected in an input direction (i.e., least significant bit side) of the AND circuit receiving the failure bit, a signal line associated with the failure bit is disconnected and signal lines are re-connected to adjacent signal lines including an extra line by selectors. Hence, a failure bit is compensated in a very simple structure.

Semiconductor memory testing device

In a normal mode, a logic test signal (LOGTEST), a RAM test signal (RAMTEST), and a shift mode signal (SM) are set to '0'. A RAM core (91) is synchronously written and asynchronously read. In a logic test mode, the RAM test signal (RAMTEST) is set to '0', and the logic test signal (LOGTEST) is set to '1'. In a RAM test mode, the RAM test signal (RAMTEST) is set to '1', and the logic test signal (LOGTEST) is set to '0'. A scan path (3a) is used both as a scan path provided between logic portions (82, 83) in the logic test and as a scan path provided at the output of the RAM core (91) in the RAM test. The scan path provides a high area utilization efficiency.

A connection circuit (CC) is formed by selectors (2,3) and a flip-flop (4). Th selectors (2,3) are switch-controlled by a test holding control signal (thld) and a shift mode control signal (sm) respectively. A scan-in terminal (si) is connected to a data input 0 terminal of the selector (2), while an output terminal of the flip-flop (4) is connected to its data input 1 terminal. An output terminal of the selector (2) is connected to a data input 1 terminal of the selector (3). An input terminal (d) is connected to a data input 0 terminal of the selector (3). An output terminal of the selector (3) is connected to an input terminal of the flip-flop (4). The output terminal of the flip-flop (4) is also connected to a scan-out terminal (so) and an output terminal (q) of the connection circuit (CC). In an ordinary operation, data is inputted through the input terminal (d). Thus, a scan path forming circuit attaining a high-speed operation in an ordinary operation is provided.

Scan path forming circuit

An address generator circuit (21A) includes a shift register (28) for storing therein address data (AD) to be outputted. A plurality of memory circuits which are equal in one of the numbers of bits of X and Y addresses for specifying rows or columns of memory cell arrays and different in the other number, apply data to scan paths so that less significant bits of the addresses having the same number of bits are stored in a position closer to an input terminal. An XOR gate (27A) in the address generator circuit (21A) generates write data (DI) for writing RAMs (31, 32) from data (X0, Y0) stored in predetermined registers of the shift register (28).

Semiconductor memory device having scan path for testing

It is an object to provide a test circuit which properly finds faults of memory cells of a storage circuit. Registers XB1, 0, YB1, 0 of a circuit SGC1 supply address data which includes four order all cycle sequence. A generating portion 10a provides '1' when data XB1, 0 are '10' and provides '0' in other cases. A generating portion 11a provides '1' when data XB1,0 are '01' and provides '0' in other cases. One of the outputs of the generating portions 10a, 11a is selected with the data YB1 and a selector S and provided to a RAM 1 as data DI. In the RAM 1, one of word lines is selected by X address data and data of memory cells MC are applied onto bit lines bit 0-3. With this structure, the logic on the bit line selected by the Y address data changes from '0' to '1' or from '1' to '0'.

It is an object to reduce circuit scale and increase operation speed of a memory test circuit which performs a memory test according to the ping-pong pattern. An address signal of a remarked cell is generated by an LFSR (76) and address signals for other cells are generated by an LFSR (75). The LFSR (76) updates the generated address signal every time the LFSR (75) generates one cycle of address signals. The address signals of the LFSR's (75, 76) are alternately switched by a selector circuit (78) and outputted to a RAM (2A).

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Tokyo, Japan

Tokuya Osawa