Fujitsu Corporation

Matsushita Electric Industrial Co., Ltd.

Pd Service Corporation

Tokushige Hisatsugu

Masaru Sasago

Masayuki Endo

Koichi Kobayashi

Makoto Kosugi

Tetsuya Ogawa

Hikou Shibayama

As shown in FIG., a multi-layer structured exposure maskof this embodiment is provided with a framemade of glass, a silicon plateprovided on an under surface of the frame, a heat absorption maskprovided on an under surface of the silicon plate, a silicon plateprovided on an under surface of the heat absorption maskand a stencil maskprovided on an under surface of the silicon plate. The stencil maskis made up of a silicon substrate and is provided with a slit-shaped patterning openingto form a resist pattern. The heat absorption maskis made up of a silicon substrate coated with an SiN film and is provided with slit-shaped openingsshaped in almost the same way as the patterning openingsof the stencil mask. The openingis shaped in such a size that will not block electron beams necessary to form a resist pattern as shown in FIG.(). That is, a size of the openingis equal to a size of the patterning openingor a size of the openingis a little larger Furthermore, the multi-layer structured exposure maskof this embodiment is provided with a large openingthat penetrates the frameand silicon plateand exposes the area of the upper surface of the heat absorption maskin which the openingsare formed. Furthermore, the multi-layer structured exposure maskof this embodiment is provided with a hollow sectionthat penetrates the silicon plateand exposes the area of the under surface of the heat absorption maskin which the openingsare formed and the area of the upper surface of the stencil maskin which the patterning openingsare formed. In the multi-layer structured exposure maskof this embodiment, the patterning openingsof the stencil maskand the openingsof the heat absorption maskare aligned in the horizontal direction as shown in FIG.().

Exposure mask, method for manufacturing the mask, and exposure method

A method and an apparatus for plasma etching semiconductor materials by providing an intermediate electrode between the electrodes in a parallel state type plasma etching apparatus, moving the intermediate electrode by a drive mechanism, and continuously changing from a condition of high input power and high self-bias voltage to a condition of low input power and low self-bias voltage while varying the distance between the intermediate electrode and the first electrode and the RF power, thereby to remove damage or deposits that may have been formed on the surface when the semiconductor material was being subjected to processing.

Method and apparatus for plasma etching

Growing community of inventors

Chofu, Japan

Tokushige Hisatsugu