Hitachi, Ltd.

Other

Renesas Technology Corp.

Showa Denko K.k.

Hitachi Vlsi Engineering Corp.

Tokuo Kure

Yoshifumi Kawamoto

Hideo Sunami

Toru Kaga

Eiji Takeda

Yoshio Sakai

Masanobu Miyao

Hideo Todokoro

Katsuhiro Kuroda

Yasushi Goto

Ken Ninomiya

Naotaka Hashimoto

Tetsuo Ono

Masayuki Kojima

Tatsumi Mizutani

Takafumi Tokunaga

ShinIchiro Kimura

Shinichiro Kimura

Tohru Nakamura

Satoru Yamada

Tadashi Otaka

Motohiko Yoshigai

Fumio Mizuno

Takashi Sato

Yoichi Tamaki

Hiroshi Kawakami

Takashi Nishida

Kazuhiko Sagara

Kazuo Nakazato

Takashi Kobayashi

Toshihiko Tanaka

Norio Hasegawa

Katsutaka Kimura

Hitoshi Kume

Digh Hisamoto

Hiroyasu Shichi

Hideyuki Kazumi

Masaru Izawa

Ken Yoshioka

Katsuhiro Shimohigashi

Toshiaki Masuhara

Osamu Minato

Yasuhiro Mitsui

Atsushi Hiraiwa

Shinji Shimizu

Naoyuki Kofuji

Hisayuki Higuchi

Masao Tamura

Yoshiki Yamaguchi

Takeo Shiba

Masahiro Moniwa

Shinichi Tachi

Hideaki Kurata

Makoto Ohkura

Yasuo Wada

Minoru Nagata

Noriyuki Homma

Tetsuya Hayashida

Takahiro Okabe

Kikuo Kusukawa

Terunori Warabisako

Akira Sato

Noboru Moriuchi

Takao Miyazaki

Koichiro Ishibashi

Masao Kondo

Kenji Saito

Yoshinobu Nakagome

Takashi Hashimoto

Mutsuko Hatano

Toshiyuki Mine

Toshiaki Yamanaka

Akihiro Shimizu

Hiromasa Noda

Katsuyoshi Washio

Aritoshi Sugimoto

Eiichi Murakami

Tetsuo Adachi

Nobuyoshi Kobayashi

Ushio Kawabe

Fumio Murai

Toshikazu Nishino

Jiro Yugami

Sadayuki Okudaira

Shinji Okazaki

Seiichi Kondo

Shinpei Iijima

Kazunori Tsujimoto

Hiromichi Enami

Tomoyuki Araki

Takahiro Onai

Yuzuru Ohji

Akihisa Uchida

Haruhiro Hasegawa

Yoshimasa Murayama

Norikazu Hashimoto

Shin'ichiro Kimura

Akitoshi Ishizaka

Yasuhiro Sugawara

Tsuyoshi Uda

A method for cleaning piping including the steps of supplying an acid to a cleaning water to prepare a cleaning water having pH of 4 or lower, mixing ozone gas to the cleaning water, and passing the cleaning water through the piping to be cleaned, or a cleaning system for piping, the system including a reservoir which retains cleaning water, an acid providing means supplies an acid to the cleaning water, an ozone generation means which generates ozone gas, a circulation flow path including a circulation pump which connects the reservoir and the ozone generation means in the form of a closed circuit, and circulates the cleaning water between the reservoir and ozone generation means, a conduction flow path including a conveying pump which communicates the reservoir and the piping to be cleaned, and conveys the cleaning water retained in the reservoir through the piping to be cleaned.

Method for cleaning piping and cleaning system for piping

A surface processing method of a sample having a mask layer that does not contain carbon as a major component formed on a substance to be processed, the substance being a metal, semiconductor and insulator deposited on a silicon substrate, includes the steps of installing the sample on a sample board in a vacuum container, generating a plasma that consists of a mixture of halogen gas and adhesive gas inside the vacuum container, applying a radio frequency bias voltage having a frequency ranging from 200 kHz to 20 MHz on the sample board, and controlling a periodic on-off of the radio frequency bias voltage with an on-off control frequency ranging from 100 Hz to 10 kHz.

Sample surface processing method

A semiconductor integrated circuit device with third gates comprising second conduction type source/drain diffusion layer regionsformed first conduction type well, floating gatesformed on semiconductor substratethrough an insulator film, control gatesformed on floating gatesthrough nitrogen-introduced silicon oxide filmand third gatesdifferent from the floating gates and the control gates, formed through the semiconductor substrates, the floating gates, the control gates and the insulator film, where the third gates are formed as filled in gaps between the floating gates existing in a vertical direction to word lines and channels and the height of third gatesthus formed is made lower than that of floating gates, has improved reduction of memory cell size and operating speed and improved reliability after programming/erasing cycles.

Semiconductor integrated circuit device and process for producing the same

A plasma processing method for etching a sample having a gate oxide film which generates a plasma in a vacuum chamber using electromagnetic waves, applies an rf bias power to the sample, turns off the rf bias power before a charged voltage of the sample reaches a breakdown voltage of the gate oxide film, turns on the rf bias power after the charged voltage of the sample has substantially dropped and repeats the turning on and off of the rf bias power to process the sample. The off-time is set at least longer than the on-time, and the plasma is generated by continuously supplying power to enable generation of the plasma during the repeated turning on and off of the rf bias power.

Surface processing method of a specimen and surface processing apparatus of the specimen

A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.

Semiconductor memory device

According to the present invention, there is provided a sample surface treating apparatus for processing a fine pattern by plasma etching, including a stage provided in a chamber, on which a sample to be subjected to a surface treatment is placed; etching gas supply source for continuously supplying an etching gas for plasma generation into the chamber; a plasma generator for generating a high-density plasma in the chamber; a bias power supply for applying a bias voltage of 100 kHz or higher to the stage independently of the plasma generation; and a pulse modulator for modulating the bias power supply at a frequency of 100 Hz to 10 kHz, wherein a surface treatment in which the minimum feature size is 1 &#x3bc;m or smaller is performed on the sample placed on the stage.

Method and apparatus for treating surface of semiconductor

A semiconductor integrated circuit device with third gates comprising second conduction type source/drain diffusion layer regions formed in first conduction type well , floating gates formed on semiconductor substrate through an insulator film , control gates formed on floating gates through nitrogen-introduced silicon oxide film and third gates different from the floating gates and the control gates, formed through the semiconductor substrates, the floating gates, the control gates and the insulator film, where the third gates are formed as filled in gaps between the floating gates existing in a vertical direction to word lines and channels and the height of third gates thus formed is made lower than that of floating gates , has improved reduction of memory cell size and operating speed and improved reliability after programming/erasing cycles.

A method and apparatus of treating a surface of a sample. A sample is arranged on a stage provided in a chamber, an etching gas is continuously supplied into the chamber and a plasma is generated from the etching gas. An rf bias at a frequency of 100 kHz or higher is applied to the stage independently of the generation of the plasma, and the rf bias is modulated at a frequency of 100 Hz to 10 kHz. Thereby, a surface treatment in which a minimum feature size is 1 &mgr;m or smaller is performed on the sample.

A plasma processing method for etching a sample having a gate oxide film includes generating a plasma in a vacuum chamber using electromagnetic waves, applying an rf bias power to the sample, turning off the rf bias power before a charged voltage of the sample reaches a breakdown voltage, turning on the rf bias power after the charged voltage of the sample has substantially dropped, and repeating the turning on and off of the rf bias power to process the sample. The off-time is set at least longer than the on-time.

Specimen surface processing method

Method for processing surface of sample

A superfine electronic device is disclosed, which is constructed by atomic fine lines having a structure in which a plurality of atoms are arranged on one or a plurality of straight lines, in a ring shape or on curves with a size of atomic level, and which includes elements for doping electrons and holes. Using these atomic fine lines, it is possible to integrate semiconductor elements utilizing pn junctions at an atomic level with a high density. A groove having a sufficiently small size is formed in an insulating film disposed on a substrate. Then, atoms or molecules are supplied on the substrate and in the groove, which and are heated to a temperature sufficiently high for moving the atoms or molecules during or after the supply thereof to form a quantum fine line at edge portions of the groove.

Superfine electronic device and method for making same

Electrical damage to semiconductor elements in the plasma etching thereof is suppressed. In processing of a fine pattern by plasma etching, the high frequency power supply to be applied to the specimen is turned off before the charge potential at a portion of the pattern reaches the breakdown voltage of the gate oxide film which is interconnected to said fine pattern, and then the high frequency power supply is turned on when the charge potential at the portion of the pattern drops substantially. This on and off control is effected in a repetitive mode of operation.

Specimen surface processing method and apparatus

A semiconductor memory having a capacitor formed by utilizing a groove formed in a semiconductor substrate and an insulated gate field effect transistor and suppressing expansion of a depletion layer from the groove, and a method for fabricating the same are disclosed. An area occupied by each memory cell can be made very small and a distance between the memory cells can also be made very small, accordingly, high density integration is facilitated.

Method for fabricating semiconductor memory with a groove

An electron beam which can transmit through part of a specimen and can reach a portion not exposing to the electron beam is irradiated and a scanning image is obtained on the basis of a signal secondarily generated from a portion irradiated with the electron beam. Dimension-measuring start and end points are set on the scanning image and a dimension therebetween is measured. A cubic model is assumed, the cubic model is modified so as to match the scanning image, and dimension measurement is carried out on the basis of a modified cubic model.

Scanning electron microscope and method for dimension measuring by using

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Tokyo, Japan

Tokuo Kure