Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Toshiba Memeory Corporation

Tokumasa Hara

Noboru Shibata

Masanobu Shirakawa

Hiroshi Sukegawa

Shirou Fujita

Hideo Kato

Hidetoshi Saito

Ikuo Magaki

Yasuhiko Honda

Masao Kuriyama

Toshikatsu Hida

Osamu Torii

Riki Suzuki

Takafumi Ikeda

Tatsuya Hiramatsu

Takahiro Suzuki

Hironori Uchikawa

Hiroshi Yao

Naomi Takeda

Hitoshi Iwai

Takayuki Akamine

Yohei Hasegawa

Shinya Fujisawa

Yoshihisa Kojima

Naoya Tokiwa

Tadayuki Taura

Kenichiro Yoshii

Hitoshi Shiga

Akira Yamaga

Tatsuhiro Suzumura

Yoshiki Saito

Toshifumi Shano

Hiroyuki Moro

Kejen Lin

Juan Shi

Keiri Nakanishi

Kohei Oikawa

Sho Kodama

Toshio Fujisawa

Shohei Asami

Kenta Yasufuku

Daiki Watanabe

Shigefumi Irieda

Kiichi Tachi

Naoto Oshiyama

Susumu Tamon

Masuji Nishiyama

Shigehiro Asano

Kosuke Hatsuda

Hidehiro Shiga

Yasuhiko Kurosawa

Ryo Yamaki

Takahiro Shimizu

Daisuke Iwai

Toshiyuki Yamagishi

Naoaki Kokubun

Tsuyoshi Atsumi

Naoto Tomita

Yu Nakanishi

Arata Miyamoto

Yasuyuki Imaizumi

Manabu Sato

Masaki Unno

Yuji Komine

Itaru Hida

Emiko Nagatani

A memory system has a nonvolatile memory which comprises memory cells capable of storing 4-bit data of first to fourth bits by sixteen threshold regions including a first threshold region corresponding to an erased state and second to sixteenth threshold regions having higher voltage levels than a voltage level of the first threshold region corresponding to a written state; and a controller which causes the nonvolatile memory to execute a first program for writing data of the first bit and the second bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit and the fourth bit. The controller controls such that the threshold region is any threshold region of a seventeenth threshold region corresponding to an erased state and eighteenth to twentieth threshold regions having higher voltage levels than that of the seventeenth threshold region corresponding to a written state.

Memory system

According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.

Nonvolatile memory and writing method

A memory system includes a memory device with a memory cell array including a first and second plane and first and second caches. A controller is configured to output status information in response to a status read command. The status information indicating the states of the caches. The controller begins a first process in response to a command addressed to the first plane if the status information indicates the first and second caches are in the ready state, and begins a second process on the second plane according to a second command to the second plane if the status information indicates at least the second cache is in the ready state.

Semiconductor memory device including a control circuit and at least two memory cell arrays

A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.

Memory system including semiconductor memory and controller

A memory system includes a nonvolatile memory which comprises a plurality of memory cells capable of storing 4-bit data represented by first to fourth bits by sixteen threshold regions, and a memory controller configured to cause the nonvolatile memory to execute a first program for writing data of the first bit, the second bit, and the fourth bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit. In fifteen boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions, a maximum value of the number of first boundaries used for determining a value of the data of the first bit, the number of second boundaries used for determining a value of the data of the second bit, the number of third boundaries used for determining a value of the data of the third bit.

Nonvolatile memory multilevel cell programming

A semiconductor memory device includes a first memory cell for storing data using at least three levels of threshold voltages, including a first level, a second level higher than the first level and a third level higher than the second level. A first word line is connected to the first memory cell. In writing of data to the first memory cell from a state where a threshold voltage of the first memory cell is the first level, a plurality of program operations and verify operations are performed, each program operation including applying a program voltage to the first word line, each verify operation including applying a read voltage lower than the program voltage. The program operations include a program operation for the second level and a program operation for the third level, and the verify operations include a verify operation for the second level, and do not include a verify operation for the third level.

Semiconductor memory device and memory system

Information processing system

According to one embodiment, a memory system includes a non-volatile memory provided with a plurality of memory cells, and a memory controller. The memory controller reads data subjected to error-mitigation encoding from the non-volatile memory, the data including determination information indicating whether or not a value is changed by the error-mitigation encoding, executes error-mitigation decoding on the read data, re-executes the error-mitigation encoding on a decoding result obtained by the error-mitigation decoding, and compares the determination information included in the read data with determination information included in data obtained by re-executing the error-mitigation encoding and outputs a comparison result.

Memory system and method of controlling non-volatile memory

A memory system includes a non-volatile memory including at least one memory cell, a buffer, and a memory controller. The memory controller acquires first data from the buffer. The first data includes a plurality of bits of data. The memory controller generates second data by performing a randomization process on the first data, generates a flag that is information used to identify an error suppression encoding process, based on the second data, and stores the flag in the buffer. The memory controller acquires third data and the flag from the buffer. The third data is 1-bit data of the first data. The memory controller generates storage data by performing the error suppression encoding process based on the acquired flag and the randomization process on the third data, and writes the storage data into the memory cell.

A memory system of an embodiment includes a memory device including a first set of cell transistors and a second set of cell transistors; and a controller configured to transmit to the memory device a first instruction and transmit to the memory device a second instruction after reception of a first request without receiving the first request again. The first instruction instructs parallel reads from the first and second sets of cell transistors, and the second instruction instructs a read from the first set of cell transistors.

Information processing system including host device and memory system

According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.

Growing community of inventors

Kawasaki, Japan

Tokumasa Hara