Yamaha Corporation

Tokio Shirakawa

Masaki Kudo

Masatsugu Okazaki

Shizuhiko Kawai

Taro Shirahama

Kyoko Ohno

Shigematsu Fujita

Tasuya Nonaka

A musical tone signal generating apparatus has waveform memory WM which stores a plurality of compressed data sets obtained by compressing, by linear prediction, sample values obtained by sampling musical tones. The musical tone signal generating apparatus has cache circuitwhich reads out compressed data from waveform memory WM within an assigned computing period in response to instructions to generate a musical tone, and decoding circuitwhich decodes the compressed data and outputs the decoded data as the data indicative of a sample value. The musical tone signal generating apparatus has CPUinputs tone pitch information indicative of a tone pitch of a musical tone which is to be generated, identifies waveform data which is to be read out by cache circuitfrom waveform memory WM and determines, in accordance with the identified waveform data, the length of the computing period which is to be assigned.

Musical tone signal generating apparatus

With no interrupt to a CPU, waveform data stored in a NAND-type flash memory are read out on a page-by-page basis to supply a buffer of a waveform memory with waveform sample data. A series of waveform data are prestored in successive pages of the intermediate buffer capable of high-speed page access thereto. Page number of a page to be read out first is set, and that page is read into a buffer in advance. Before completion of readout of the first page, another page to be read out next is loaded into the buffer. After that, the page number is incremented by one each time readout of one page is completed, and the waveform sample data of the page number continue to be reproduced while being read into the buffer.

Tone generation apparatus

Compressed waveform data structure is proposed which is suited for segmentation of a plurality of samples of compressed waveform data into a plurality of frames and subsequent storage of each of the frames. The number of bits per sample of the compressed waveform data is variable between the frames, but uniform, i.e. the same among all of the samples, within each of the frames. Each of the frames has a same data storage size. Each of the frames includes, in a predetermined layout, an auxiliary information area for storing auxiliary information that includes compression-related information to be used for decompressing the compressed waveform data, and a data area for storing a plurality of samples of the compressed waveform data of the frame with each of the samples comprising a same number of bits. Thus, respective start positions of the frames and compressed waveform data in a memory can be fixed at predetermined positions common to the frames, so that readout control can be performed with ease.

Compressed data structure and apparatus and method related thereto

Compressed waveform data structure is proposed which is suited for segmentation of a plurality of samples of compressed waveform data into a plurality of frames and subsequent storage of each of the frames. The number of bits per sample of the compressed waveform data is variable between the frames, but uniform, i.e. the same among all of the samples, within each of the frames. Each of the frames has a same data storage size. Each of the frames includes, in a predetermined layout, an auxiliary information area for storing auxiliary information that includes compression-related information to be used for decompressing the compressed waveform data, and a data area for storing a plurality of samples of the compressed waveform data of the frame with each of the samples comprising a same number of bits.

In a sound source apparatus, a central processing unit is integrated in a semiconductor chip and operates in response to a primary operating clock signal for creating a control message. A tone generating unit is integrated in the same semiconductor chip and operates in response to a secondary operating clock signal for generating a musical tone according to the control message. A master clock generator generates a master clock signal having a desired frequency selected from a plurality of frequencies. A mode changer designates one of a first mode and a second mode corresponding to different operating speeds. A clock generator is provided for variably frequency-dividing the master clock signal to generate the primary operating clock signal and the secondary operating clock signal. The clock generator is responsive to the mode changer for changing a frequency ratio of the primary operating clock signal to the secondary operating clock signal between the first mode and the second mode. An external memory is provided separately from the semiconductor chip for storing information required for generation of the musical tone. A memory controller is provided for allotting a primary time slot to the central processing unit and a secondary time slot to the tone generating unit such as to optimize access to the external memory shared by the central processing unit and the tone generating unit. A cache memory is provided to speed up operation of the central processing unit.

Sound source chip having variable clock to optimize external memory

A control circuit is integrated in a semiconductor chip for controlling operation of an electronic musical instrument according to a custom program stored in an external memory so as to generate a musical tone. In the control circuit, an internal memory is formed in the semiconductor chip separately from the external memory for permanently storing a common program which is dedicated to synthesis of the musical tone while the custom program stored in the external memory is customized for the operation of the electronic musical instrument. A tone synthesizer is formed in the same semiconductor chip for synthesizing -,he musical tone when the common program is executed. A central processor is formed in the same semiconductor chip integrally with the tone synthesizer and the internal memory for executing the custom program to control the operation of the electronic musical instrument and for executing the common program to effectuate the synthesis of the musical tone to generate the same sequentially in response to the operation of the electronic musical instrument.

Universal microcomputer chip for electronic musical machine

Reading of a waveform memory is controlled and one of different processing is performed depending upon which of a first mode and a second mode has been designated. When the first mode has been designated, an interpolation operation is performed on the basis of plural sample value data read from the waveform memory by using a predetermined number of processing time slots and a resulting one waveform sample value data is produced. When the second mode, has been designated, a processing for producing one waveform sample value data is performed on the basis of one sample value data read from the waveform memory by using one processing time slot. By using a predetermined plural number of processing time slots, one waveform sample value data produced with a high accuracy in the first mode whereas plural waveform sample value data are produced in the second mode whereby generation of a waveform can be performed efficiently by properly utilizing the mode.

Waveform generation device capable of reading waveform memory in plural

An addition section and a memory section for storing data to be inputted to the addition section are provided. A processing section variably performs a logical processing on output data of the memory section in accordance with a control signal and gives the data to the addition section. A control section controls introduction of data to the memory section and supply of the control signal to the processing section in correspondence to respective desired operations so that plural kinds of operations for tone signal generation may be respectively performed. With this arrangement, the addition section can be shared for various kinds of operations for the tone signal generation. Consequently, operation circuits for performing the various operations are integrated, so as to realize a substantial reduction of circuitry construction.

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Hamamatsu, Japan

Tokio Shirakawa