Matsushita Electric Industrial Co., Ltd.

Tokikazu Matsumoto

Takashi Inoue

Hiromu Kitaura

Nobuyuki Ogawa

Yukio Nakagawa

Fumiaki Koga

Masahiro Honjo

Masao Tomita

Yasuhito Fukui

Masaaki Kobayashi

Hideyuki Ohgose

Haruo Ohta

Takashi Masuno

Toyohiko Matsuta

Kouichi Igata

Manabu Yumine

Shinich Uchiyama

Hiroshi Fujioka

In addition to image information recorded in a disc, &ldquo;n&rdquo; pcs. of selection lists which have their own proper numbers are recorded on the disc. Also, an address list of information stored outside of the disc is recorded on the disc. Each selection list has addresses of inside information of the image information recorded on the disc, one or more selection numbers, and their corresponding selection lists. The address list has selection list identification numbers and addresses corresponding to the selection list identification numbers. During the regular playback operation&mdash;playing back the image information recorded on the disc&mdash;when a user gives an instruction of selecting outside information, the user can get the address of the outside information from the now used selection list by retrieving the address list.

Information processor, information processing method and information recording medium on which information processing method is recorded

A video signal with superimpose character data reproducing apparatus reproduces MPEG compressed video signal from a CD-ROM. The compressed video signal read from the disc includes a plurality of blocks each having a header with a character data. The compressed video signal is expanded by an expander to a plurality of component signals, which are then modulated in modulator to a composite video signal. An extractor extracts the character data and temporarily stores it in flop-flops. The extracted character data is serially inserted in the composite video signal by synthesizer in a predetermined timing.

Video signal with super impose character data reproducing apparatus

A driving apparatus for a liquid crystal display of a type sandwiching a layer of liquid crystal material capable of responding to a voltage of an effective value applied between row and column electrodes. The apparatus includes an image data buffer memory for storing and outputting a digital image data of one frame, transferred from an external circuit, in the form of an image data matrix; a matrix generator for outputting data having a predetermined orthogonal matrix; a converter for converting the image data with the use of the orthogonal matrix into an converted data matrix and for outputting the converted data matrix; a converted data buffer memory for storing and outputting the converted data matrix; a driver for driving the liquid crystal display in synchronism with a row signal, which applies the orthogonal matrix to the row electrodes of the liquid crystal display, and also a column signal which applies the converted data matrix to the column electrodes of the liquid crystal display.

Driving apparatus for liquid crystal display

A driving apparatus for driving a passive matrix liquid crystal display utilizing an active driving method includes an image buffer storage for storing one frame of image data in the form of a matrix to output image data on a column by column basis to produce a rearranged image data. A matrix generator generates row data. A data converter multiplies the rearranged image data with row vectors to produce converted data. A converted data buffer storage stores the converted data and outputs the data on a row by row basis to produce a column data. A LCD driver is provided for producing a column signal based on the column data and a row signal based on the row data, and further for applying these row and column signals to row and column electrodes, respectively, to drive the LCD.

A time base correcting apparatus for reducing hindrance to a carrier chrominance signal due to clock jitter, when a sampling clock is generated by a digital circuit. In the time base correcting apparatus, a video signal is sampled with a clock synchronized with the video signal to be written to an FIFO memory. The video signal is then read out therefrom with a fixed clock to remove time base changes of the video signal. The fixed read clock is generated by multiplying two different frequency signals together, where one of the signals has a lower frequency approximately equal to (n+1/4) f (where n is an arbitrary integer, and f is a horizontal sync frequency) and using one of the resultant sidebands obtained through use of a bandpass filter. The read clock frequency is separated by 1/2 f from the other sideband frequency to reduce hindrance between the signals, and in turn to reduce viewable hindrances during the display of the video signal read out from the FIFO.

Apparatus for rejecting time base error of video signal

A video signal having a residual error superposed in the horizontal synchronizing signal period is received from a time axis error correcting circuit for suppressing the time axis error of video signal, and the residual error superposed portion is replaced with a specific data.

Video signal processing apparatus having timebase corrector and means

An input video signal is converted into a digital signal by a clock of a predetermined time interval. Of the time base errors included in the above signal, time base errors of the clock unit are corrected by resetting the write address of the memory, and time base errors of less than the clock unit and velocity errors are corrected by an interpolation filter provided at a later stage of the memory. By the above processing, it is possible to correct time base errors by only a clock of a predetermined interval and it is also possible to improve interface characteristics with other digital processing sections.

Time base corrector

In a phase error detector for detecting a phase error .theta. of an input color burst signal from a phase of a reference signal from sin .theta. component and cos .theta. component, if either one of the sin .theta. component and cos .theta. component requires M bits for its expression, the both values are divided by a same value to shift in bits to be expressed in N bits (N&lt;M), thereby preventing the subsequent circuit from increasing in scale.

Circuit for detecting phase error of color burst signal

A time base correcting circuit is provided in which a time base error in a video signal is corrected by converting the video signal to a digital form which is then recorded into a memory with a write-in clock signal synchronized with a horizontal synchronizing signal or a color burst signal carried in the video signal, reading the digital signal with a read-out clock signal generated from a reference clock signal, and converting it into an analog form. In particular, a velocity error data is added to a corresponding horizontal blanking period of the video signal and after processing of the signals having time delays and continuation errors in the time base, the velocity error data is extracted from the horizontal blanking period of the video signal. Then, the read-out clock signal is phase modulated with the velocity error data extracted and used for correction of the velocity error in the video signal of analog form converted from its digital form.

Time base corrector having a velocity error data extracting circuit

In a system for eliminating time base fluctuation of a video signal having a synchronizing signal and a burst reproduced from a video disk, for example, the synchronism is first coarsely pulled in on the basis of the horizontal synchronizing signal and then precisely follows the time base fluctuation on the basis of the burst signal. A shift of the output synchronizing signal is corrected by using a phase detection of an input horizontal synchronizing signal when an output synchronizing signal is produced on the basis of the read address of a memory for eliminating time base fluctuation, thereby preventing, for example, a superimposed character using the output synchronizing signal from fluctuating on a picture.

Synchronizing phase shift corrected synchronous signal detecting

A digital phase locked loop for correcting the phase of an output signal with respect to an input signal has a phase comparator for comparing the phases of the input signal and a feedback signal from a variable frequency oscillator. The output signal of the phase comparator representing the phase difference is integrated in a low pass filter. The output of the low pass filter is supplied to a switch which alternately selects between the output of the low pass filter and a zero level signal from a zero generator. The output of the switch is supplied to the variable frequency oscillator. The output signal of the variable frequency oscillator is returned to the phase comparator, so that the phase of the output signal from the variable frequency oscillator is synchronized with the phase of the input signal.

Digital phase locked loop for correcting a phase of an output signal

A video signal is sampled with a sampling frequency which is at least four times of the highest frequency of the video signal, subsequently, sampled signals are converted into digital signals and component thereof which are higher than the highest frequency of the video signal are eliminated by a low pass filter, then, remaining sampled signals are alternately decimated by a decimation circuit, thus the sampling frequency is reduced in appearance to the half thereof.

Digital video signal processing method and apparatus therefor

A digital automatic gain control apparatus is provided which controls gain such that when an analog video signal is converted into digital signals for processing, the input of the A-D converter is maintained at a fixed level, and after the analog signal has been converted into digital form, the output of the digital system circuit is also maintained at a fixed level. In this apparatus, an input signal is passed through an analog variable gain amplifier, the signal is converted into digital form, and the output of an A-D converter is passed through a digital variable gain amplifier. The amplitude level of the output of the digital variable gain amplifier is detected by an amplitude detecting unit and is controlled so as to be equal to a specified reference value. At this time, the analog variable gain amplifier is controlled so that the level of the control signal for controlling the digital variable gain amplifier is equal to a specified reference value, thereby maintaining the signal of the A-D converter at a fixed level. Gain control of the analog signal system and the digital signal system, before and after the A-D converter, is effected by a single amplitude detecting unit.

Digital automatic gain control apparatus

A disclosed time base corrector comprises a clock generater for generating a clock signal whose period is fixed, an analog-to-digital converter for sampling amplitude values of an input analog signal having a time base error at sampling points given by the clock signal, an adaptive interpolation filter for interpolating a correct amplitude value at a resampling indicated by a resampling position signal, a resampling position signal producing circuit for detecting the time base error and producing from the detected error the resampling position signal, and a digital-to-analog converter for converting the interpolated amplitude values to an analog signal which has no time base errors. The time base correction is implemented by pure digital signal processing without any analog signal processing. The time base corrector does not use such a clock signal that has time base fluctuations.

A video signal processing apparatus incorporates a 1H or 2H delay circuit, wherein H is a horizontal synchronization period. The output of the delay circuit is fed back to the input thereof so as to average the noise, thus raising the signal S/N ratio. The feedback line includes a nonlinear processing circuit which has a small gain when the signal input has a low vertical correlation, whereby the signal S/N ratio is improved without causing the delay of the color signal in the vertical direction nor the deteriorated resolution of the luminance signal.

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Osaka, Japan

Tokikazu Matsumoto