Hitachi, Ltd.

Hitachi Tobu Semiconductor

Tohru Yoshida

Kunihiko Nishi

Atsushi Nakamura

Toshio Sugano

Aizo Kaneda

Masayuki Watanabe

Seiichiro Tsukui

Yoshiaki Wakashima

Michio Tanimoto

Suguru Sakaguchi

Michiharu Honda

Takeshi Komaru

Kohji Nagaoka

Kohji Serizawa

Katsuro Wakai

Jiro Imamura

There is a trend to increase that area of a device requiring a memory of large capacity, which is occupied by a semiconductor memory. This trend obstructs reduction of the size of the device. The present invention contemplates to provide a memory which can have a high integration, a high density and a large capacity while minimizing the mounting area. In order to achieve this memory, the TAB (Tape Automated Bonding) of the prior art is mounted on an electrically conductive connector, and a plurality of structures composed of the TAB and the connector are stacked. Moreover, the connector mounting the TAB thereon is constructed such that the independent terminals of the stacked TABs may not be shorted.

Stacked semiconductor memory device and semiconductor memory module

Semiconductor stacked device

Semiconductor device and semiconductor module with a plurality of

In a multiprocessor system in which a plurality of instruction processors (IP's) share a main storage (MS) and a channel controller (CHC) through a system controller (SC), when an I/O interrupt request is issued, IP's connected to the SC are examined to determine whether each of the IP's is executing an instruction which permits acceptance of the I/O interrupt request during the execution of the instruction. If one of the IP's is not executing such an instruction and can accept the I/O interrupt request, that IP will be selected.

I/O interrupt handling mechanism in a multiprocessor system

Growing community of inventors

Yamato, Japan

Tohru Yoshida