Hitachi, Ltd.

Hitachi Microcomputer Eng. Ltd.

Hitachi Microcomputer System, Ltd.

Hitachi, Vlsi Eng. Corp.

Tohru Shonai

Yooichi Shintani

Eiki Kamada

Kiyoshi Inoue

Kazunori Kuriyama

Shigeo Takeuchi

Kouji Nakamura

Tooru Hiraoka

Akira Yamaoka

An information processing apparatus in which instructions are processed one by one conceptually and results thereof are conceptually orderly written into a memory comprises an instruction control circuit capable of decoding M instructions and reading operands in parallel, N (N.gtoreq.M) execution circuits capable of executing a plurality of instructions mutually in parallel, a detection circuit for determining whether all of M execution circuits of the N execution circuits required by the M instructions decoded by the instruction control circuit are vacant or not, and a reserve circuit for reserving the execution of the M decoded instruction while the detection fails to detect sufficient vacancy.

Information processing system and information processing method for

A method and apparatus for controlling a conditional branch instruction in a pipeline type data processing apparatus which are adapted to judge whether or not a conditional branch instruction is valid, judge whether or not a condition code necessary for a taken/not-taken judgement made for the conditional branch instruction is valid, and selectively make a taken/not-taken judgement for the conditional branch instruction in accordance with the results of the judgements made to the conditional branch instruction and the condition code.

Method and apparatus for controlling conditional branch instructions for

An information processing method and apparatus for applying pipeline control and an advanced control to a sequence of instructions to be executed. The instruction sequence contains a plurality of conditional branch instructions. The apparatus includes a section for sequentially holding therein each instruction of the sequence of instructions to be input in a manner like a pipeline operation; an arithmetic section for obtaining a result of an operation of an instruction associated with each of the plural conditional branch instructions of the instruction sequence and selecting, from the associated instruction, instructions for which an advanced operation is possible so as to attain an operation result for each of the instructions thus selected; a holding section for holding therein either one of the operation result attained for each of the associated instructions and the operation result obtained in advance and outputting, at an execution of an objective conditional branch instruction selected from the plural conditional branch instruction; the operation result of a particular instruction corresponding to the objective conditional branch instruction, and a judge section for comparing branch control information of the objective conditional branch instruction with the operation result outputted from the holding means to judge a branch success or failure for the objective conditional branch instruction so as to decide a next instruction to be executed in accordance with the objective conditional branch instruction.

Information processing apparatus using an advanced pipeline control

An information processor detects a conflict between successive instructions by determining whether a preceding instruction under execution calls for fetching a first operand from a main memory, generating execution result data based on the first operand and updating one of a plurality of address data designated by a to-be-executed succeeding instruction, with the execution result data. When a conflict is detected, there is supplied to an address adder at least some of the plurality of address data determined by a type of the preceding instruction to complete an operand address calculation stage for the succeeding instruction. Then, before the one address data is updated by the preceding instruction after the first operand has been fetched from the main memory in an operand fetch stage for the preceding instruction, an operation determined by the preceding instruction is performed on the output of the address adder and the fetched first operand to generate an address equal to a sum of the plurality of address data, excluding said one address, and the execution result data for the preceding instruction, and this address is used as the address of the second operand of the succeeding instruction.

Information processor providing enhanced handling of address-conflicting

Data processor for concurrent executing of instructions by plural

A data processor includes an instruction detection unit for detecting that a succeeding instruction writes a read-out operand into a general register group without subjecting it to arithmetic or logical operation, in accordance with instruction decode informations provided by an instruction hold unit; a conflict detection unit for detecting a conflicting state that the preceding instruction performs a write operation into a general register of the general register group and the succeeding instruction reads an operand from the same general register, in accordance with instruction decode informations provided by the instruction hold unit; and a contention detection unit for detecting a contention state that the preceding instruction performs a write operation into the same general register and the succeeding instruction also performs a write operation into the same general register, in accordance with instruction decode informations provided by the instruction hold unit.

Data processor for parallelly executing conflicting instructions

A pipelined data processor comprises a circuit for storing two instructions in a pair of instruction registers, a circuit for detecting whether those instructions are a combination of an instruction requesting the use of an operation unit and an instruction requesting the use of another resource, and a circuit to control the execution of the instructions when the decision of the detection circuit is affirmative such that those instructions are executed by the operation unit and the resource in a plurality of stages.

Pipelined data processor capable of decoding and executing plural

An information processing apparatus for executing instructions in parallel includes circuitry which, when a first instruction requesting reading of an operand from a certain address of the main storage or buffer storage has been decoded, detects among instructions in execution the presence of a second instruction requesting writing of an operand held by a register such as a general-purpose register into that address of the main storage without implementing an operation on the operand. If the second instruction has been detected, the invention reads out an operand from the register specified for operand reading by said second instruction before operand writing into the main storage by the second instruction is completed.

Information processing apparatus for determining sequence of parallel

A buffer or a plurality of buffers are provided each for holding a write address and an address specifying a write position which are obtained as a result of an execution based on a predicted result. The execution of the instruction is continued up to the operation stage regadless of whether or not the instruction is being executed in the predicted state, the data and the write address are held in the buffer written. The data in the buffer is canceled if the prediction is found to be wrong when the predicted state is completed, and the data is utilized if the prediction is found to be correct.

Data processor capable of executing instructions under prediction

In accordance with the invention, there are disposed a logical register group and a physical register group. Direct access is made to the logical register group on the basis of a register number designated by an instruction. To make access to the physical register group, there is disposed a circuit which converts the register number designated by the instruction to a physical register number. A plurality of arithmetical or logical operation units (ALUs) are disposed to execute a plurality of instructions in parallel. There is further disposed a circuit which supplies an operand data from the physical register group to each ALU and writes the operation result data of each ALU into the physical register group and into the logical register group. When a write register number designated by a preceding instruction A and a succeeding instruction B has the same value a, mutually different physical register numbers b' and b' are determined with respect to the write register number a for both instructions A and B. Therefore, the instruction B can be executed in parallel with the instruction A before the operation of the instruction A is complete.

Data processor having a plurality of operating units, logical registers,

A data processing device which is equipped with a plurality of arithmetic units so that a plurality of instructions may be processed in parallel by the plural arithmetic units. The device includes a register control circuit for assigning one of a plurality of physical registers to store instructions when more than one of the instructions requires the use of the same logical register. This correspondence between the physical and logical registers is maintained while instructions are subsequently transferred to the arithmetic units where they are processed in parallel.

Growing community of inventors

Hadano, Japan

Tohru Shonai