Hitachi, Ltd.

Renesas Electronics Corporation

Tohru Nojiri

Keiji Kojima

Kiyokazu Nishioka

Kazuhiko Tanaka

Yoshifumi Fujikawa

Tan Watanabe

Masao Ishiguro

Tatsuya Saito

Keiichi Kurakazu

Jun Okitsu

Keisuke Toyama

Yugo Kashiwagi

Yuki Kondoh

Kaoru Kato

Yasunori Kaneda

Takeshi Kato

Eiichi Suzuki

Shumpei Kawasaki

Yoshiki Kurokawa

Koichi Terada

Masahiro Kainaga

Chiaki Hirai

Kousuke Sakoda

Masayoshi Mase

Yuki Kuroda

Shunpei Kawasaki

Chisa Nagai

Yukiko Morimoto

Norihisa Suzuki

Display screen with graphical user interface

Pieces of working information on workloads, positions of the workloads, pieces of environmental information on cooling facilities, and positions of the cooling facilities are stored as arrangement information. The pieces of working information on the workloads are estimated, and allocation of tentative workloads is deduced for fear the pieces of working information may exceed the performances of a group of information processing devices. Tentative power consumptions and arrangement information resulting from the allocation of the tentative workloads, and tentative power consumptions and arrangement information necessary for the allocation of the tentative workloads are calculated. Tentative cooling powers required to control the cooling facilities are calculated. Allocation of the tentative workloads minimizing the sum total of the tentative power consumptions of the information processing devices and the tentative cooling powers of the cooling facilities is searched. Based on the searched allocation, the workloads are allocated to the information processing devices.

Information processing system, and its power-saving control method and device

An information processing system which determines an allowable temperature of intake air to an information processing apparatus based on information of a temperature of intake air to the information processing apparatus, information of a temperature of exhaust air of the information processing apparatus, information of a power consumption of the information processing apparatus, and information of an allowable temperature of exhaust air of the information processing apparatus to thereby save power of the information processing system.

Information processing system, operation management method of information processing system, and data center

This invention is intended to reduce the hypervisor overhead. In the data processor disclosed herein, when a device driver calls for access to a control register to activate a process of a dedicated controlled peripheral device, the access is handled directly without intervention of processing by the hypervisor. When an interrupt is generated from a dedicated controlled peripheral device, a process is directly initiated by the device driver of the operating system governing the peripheral device without intervention of processing by the hypervisor. By implementing this manner of control in the processor, it becomes possible to carry out peripheral device control without intervention of processing by the hypervisor. Thereby, the hypervisor overhead is alleviated.

Data processor with interfaces for peripheral devices

The data processor can form a system including a combination of two or more operating systems running in parallel, which achieves a higher data transfer rate between operating systems and the increase in system performance without impairing the system reliability. In the system, data transfer between domains is performed in an enhanced access mode as well as an access mode in which an access from a domain manager having control of domains is handled as one from the domain manager. The enhanced access mode is arranged by enhancing, to a CPU scale, an access mode in which an access from the domain manager is treated as an access from a software program working on a domain, and the software program of domain manager transfers data between the domains. For example, in case that the domain manager performs data transfer between domains in the enhanced access mode, a read access from the domain manager is disguised as a read access from a first domain, and a write access from the domain manager is disguised as a write access from a second domain.

Data processor

A network topology management system includes information processing units, storage units, connection units that control connection switching between the information processing units and the storage units, a management unit that manages a network topology consisting of the information processing units, the storage units and the connection units, and an emulator connected to the connection units and to the management unit of the network. The emulator comprises a conversion section that converts first equipment identification information that identifies the information processing units or the storage units into second equipment identification information that is recognizable by the management unit to identify the information processing units or the storage units, and a transmitting section that sends the second equipment identification information to the management unit. The management device has a control section that manages the network topology based on the second equipment identification information.

Network topology management system, management apparatus, management method, management program, and storage media that records management program

In the case of constituting a processing unit having the characteristic of a VLIW type processing unit and the characteristic of a pipeline type processing unit, since reference to the result of operations is made among a plurality of processing units executing in parallel the operations, transfer of the register file is frequently generated among the processing units, resulting in insufficient effect of the high speed operations. In view of solving this problem, the predicate registers are provided and moreover a means for broadcasting the update data of the predicate register to all processing units is also provided. Thereby, operations for obtaining branching condition and numerical value can be realized in different processing units and the number of steps of the processing program can be reduced. In addition, since high speed transfer between the processing units of the data register having a wider bit width is no longer required and thereby the mounting area can be reduced and high speed processing unit can be realized.

VLIW system with predicated instruction execution for individual

Each processing unit 110a to 110d has an individual cache memory 100a to 100d. When the cache memories read an instruction from a main storage 5, an instruction field is distributed to the cache memories. Each cache memory is controlled by a common control circuit 20. A compiler operates to schedule the processes so as to focus the processes to be executed on a specific processing unit. According to the scheduled processes, the volumes of the cache memories 100a to 100d are specified according to each execution ratio of the corresponding processing units to the cache memories. In the foregoing arrangement, a processor provides the processing units controlled by a sole program counter and improves processing by improving the efficiency of the cache memory. Further, the processor improves the efficiency of the cache memory by deleting unnecessary codes.

Parallel processing unit with cache memories storing NO-OP mask bits for

A unit for efficiently carrying out a comparison operation and making it possible to prevent a generation of a disturbance in a pipeline during a pipeline operation is provided. This unit includes a first storage unit for storing storage information on two data to be compared, kind of comparison operation and result of comparison operation respectively, a second storage unit for storing said two data, kind of comparison operation and result of comparison operation, an operating unit for carrying out a predetermined plurality of kinds of comparison operations for two data, a selecting unit for selecting any one of results of comparison operation, and a processing unit for carrying out a processing of a comparison operation. The processing unit checks a storage destination of two data to be compared, gives the two data to the operating unit, checks a storage destination of a kind of a comparison operation, controls the selecting unit to select a result of an operation corresponding to the kind of comparison operation, and stores the operation result into a storage destination in the second storage unit.

Comparison operating unit and graphic operating system

An object of the present invention is to provide a processor which can execute calculation between data of a data length larger than the data length of the register file at high speed without the cost of the hardware being increased so much and the first long register 12 and the second long register 13 having a bit width which is two times of the bit width of the register file and the long register update device 14 for updating the data of the second long register 13 partially are installed between the register file 2 and the pixel calculator 11. When the long register update pixel calculation instruction is stored in the instruction register 31, the long register update device 14 connects a part of the data of the second long register 13 and a part of data read from the register file 2 and sends them to the pixel calculator 11 and the second long register 13 via the selector 15. The pixel calculator 11 executes calculation between the data of the first long register 12 and the data given from the selector 15.

Processor and data processor

There is provided an instruction supply unit 20 for generating addresses for each instruction when an interrupt occurs, from an interrupted instruction until an instruction to be executed later by the number of instructions contained in a delay slot of the instruction an interrupt control unit 50 for storing each address thus generated, and an instruction executing unit 30 for successively reading out each of the stored addresses from the address of the interrupted address after the interrupt processing is completed. The instruction executing unit 30 executes a branch instruction to the address which is first read out. Thereafter, with respect to the addresses which are read out secondly and subsequently, if the address is the branch destination address of the branch instruction, the instruction executing unit 30 executes the branch instruction to the address, and if the address is not the branch destination address, it executes an NOP instruction. Accordingly, even when the instruction length is not fixed, the interrupt can be accurately processed.

Pipeline processor including interrupt control system for accurately

In a computer system equipped with a large number of registers which have an access time much shorter than that of a main memory, a register designating address part in which the assignment of an area register having a register address of a register area as its value and the assignment of a register displacement value expressing a relative register address within the register area are combined is provided in each instruction so that, even when physical registers are increased, save and restore of registers attendant upon task switches, etc. may be lessened to attain a raised speed of program run processing. Besides, an address part for designating the main memory is provided in the same instruction.

RISC system with instructions which include register area and

In a computer system equipped with a large number of registers which have an access time much shorter than that of a main memory, a register designating address part in which the assignment of an area register having a register address of a register area as its value and the assignment of a register displacement value expressing a relative register address within the register area are combined is provided in each instruction so that, even when physical registers are increased, save and restore of registers attendant upon task switches, etc. may be lessened to attain a raised speed of program run processing. Besides, an address part for designating main memory is provided in the same instruction.

Data processing system having multiple register management for call and

In order to divide a memory addressed unidimensionally into a plurality of memory areas and to manage efficiently these memory areas, the address to be accessed inside the memory is determined on a software basis by a computer instruction by use of the value of a first pointer designating each memory area and the value of a second pointer designating the relative address in the designated memory area.

Growing community of inventors

Tokyo, Japan

Tohru Nojiri