Hitachi, Ltd.

Sumitomo Chemical Company, Limited

Sciocs Company Limited

Hosei University

Other

Hitachi Device Engineering Co., Ltd.

Nippon Chemical Industrial Co., Ltd.

Director-general of the Agency of Industrial Science and Technology

Railway Technical Research Institute

Tohru Nakamura

Kazuo Nakazato

Minoru Nagata

Takahiro Okabe

Katsuyoshi Washio

Takahiro Onai

Kazuhiko Sagara

Tokuo Kure

Noriyuki Homma

Tetsuya Hayashida

Takao Miyazaki

Takeo Shiba

Masatada Horiuchi

Yoichi Tamaki

Tomoyoshi Mishima

Kiyoji Ikeda

Masaharu Kubo

Tomonori Tanoue

Kenji Kaneko

Yutaka Okada

Mitsuo Nanba

Motoaki Matsumoto

Susumu Takahashi

Masao Kondo

Hiroshi Ohta

Fumimasa Horikiri

Hiroshi Masuda

Tomoyuki Watanabe

Masao Kawamura

Ichiro Imaizumi

Masahiko Ogirima

Toru Toyabe

Yasuhiro Yamamoto

Masatoshi Matsuda

Takeshi Kato

Masataka Kato

Naoki Yamamoto

Eiichi Murakami

Hiroaki Nambu

Yoshihisa Fujisaki

Nobuyoshi Natsuaki

Kazuhiro Mochizuki

Masanobu Miyao

Kazuo Kanetani

Hisayuki Higuchi

Wasao Takasugi

Kunihiko Yamaguchi

Youji Idei

Akihisa Uchida

Kenichi Ohhata

Kazuhiro Ohnishi

Yokichi Itoh

Naoki Kaneda

Akitoshi Ishizaka

Mitsuo Takeda

Takashi Uchino

Noriyuki Honma

Yoshinori Shono

Yoshiaki Sakurai

Norio Anzai

Hideki Kotaki

Hitoshi Koshimizu

Toshihiko Morishita

Takanori Nishimura

Takashi Agatsuma

Yukihiro Kiyota

Hidenobu Tatematsu

Taroh Inada

Tooru Haga

Shojiro Sugaki, Deceased

Kunihiko Watanabe

Kikuo Watanabe

Nakazato Kazuo

Masayoshi Saitoh

A semiconductor device includes a semiconductor member having a mesa structure in which a first semiconductor layer and a second semiconductor layer are laminated on each other and having a pn junction; an insulating film disposed on a side surface of the mesa structure and on an outside upper surface of the mesa structure; a first electrode connected to the second semiconductor layer on the upper surface of the mesa structure, and extends on the side surface of the mesa structure and on the outside upper surface of the mesa structure on the insulating film; and a second electrode connected to the first semiconductor layer on a lower surface of the first semiconductor layer, and having a capacitance of the insulating film when a reverse bias voltage is applied between the first electrode and the second electrode, so that a first voltage applied to the insulating film between a corner position (a first position) where the side surface of the insulating film disposed on the side surface of the mesa structure and the upper surface of the insulating film disposed on the outside upper surface of the mesa structure are connected to each other, and a corner position (a second position) where the side surface of the mesa structure and the outside upper surface of the mesa structure are connected to each other, is equal to or smaller than a second voltage applied to the first semiconductor layer between a pn junction interface (a third position) in a lower part of a region where the first electrode is in contact with the second semiconductor layer, and a position directly under the third position (a fourth position) at a height of the second position.

Semiconductor device

There is provided a semiconductor device, including: a semiconductor member having a mesa structure in which a second semiconductor layer having one of a p-type conductivity type and an n-type conductivity type is laminated on a first semiconductor layer having the other one of the p-type conductivity type and the n-type conductivity type, so that the second semiconductor layer is exposed on an upper surface of the mesa structure, a pn junction interface is exposed on a side surface of the mesa structure, and the first semiconductor layer is exposed on an outside upper surface of the mesa structure; an insulating film disposed on a side surface of the mesa structure and on an outside upper surface of the mesa structure; a first electrode electrically connected to the second semiconductor layer on the upper surface of the mesa structure, and extends on the side surface of the mesa structure and on the outside upper surface of the mesa structure on the insulating film; and a second electrode electrically connected to the first semiconductor layer on a lower surface of the first semiconductor layer, wherein the insulating film is constituted including a first insulating layer and a second insulating layer, the first insulating layer is disposed so as to cover a corner portion where the side surface of the mesa structure and the outside upper surface of the mesa structure are connected to each other, the second insulating layer is disposed so as to cover the pn junction interface exposed on the side surface of the mesa structure, or is disposed to constitute an entire thickness of the insulating film directly under the electrode end of the first electrode so as to cover the area directly under the electrode end, the relative dielectric constant of the second insulating layer is equal to or larger than the relative dielectric constant of the semiconductor member, and the relative dielectric constant of the first insulating layer is smaller than the relative dielectric constant of the second insulating layer.

There is provided a semiconductor multilayer structure, including:

Semiconductor multilayer structure and method of manufacturing the same

An integrated optical waveguide device includes a substrate, and an optical waveguide which is formed in the form of projection or is formed in a trench formed in the substrate. Each optical waveguide has a first optical area made of a first optical material and a second optical area which is made of a second optical material and is surrounded by the first optical area. The optical waveguides are arranged on both side faces of the projection or trench.

Integrated optical waveguide device

A hetero-junction bipolar transistor having an emitter composed of a semiconductor having a wider forbidden band width than that of a semiconductor constituting a base is disclosed. In the transistor, the emitter and the electrode leader area composed of a single crystalline semiconductor are provided being extended from the upper part of the emitter to the surface of the base through an insulating layer, for the purpose of making it possible to miniaturize the transistor and to operate the transistor at a high-speed by decreasing the emitter resistance.

Hetero-junction bipolar transistor and semiconductor devices using the

There is disclosed a shampoo composition including at least one particular pyrethroid compound as an active ingredient and a combination of particular nonionic surfactants. Also disclosed is a process for producing the shampoo composition.

Low-irritant shampoo composition

Disclosed is a semiconductor device using a polycrystalline compound semiconductor with a low resistance as a low resistance layer, and its fabrication method. The above polycrystalline compound semiconductor layer is doped with C or Be as impurities in a large amount, and is extremely low in resistance. The polycrystalline compound semiconductor layer is formed by either of a molecular beam epitaxy method, an organometallic vapor phase epitaxy method and an organometallic molecular beam epitaxy method under the condition that a substrate temperature is 450.degree. C. or less and the ratio of partial pressure of a V-group element to a III-group element is 50 or more. In the case that the above polycrystaline compound semiconductor layer with a low resistance is used as an extrinsic base region of an heterojunction bipolar transistor, since the extrinsic base region can be formed on a dielectric film formed on a collector, it is possible to reduce the base-collector capacitance, and hence to enhance the operational speed of the heterojunction bipolar transistor.

Semiconductor device and its fabrication method

A cement additive for inhibiting concrete deterioration contains as an effective component a powder mixture of an inorganic cation exchanger, such as a highly calcium-substituted zeolite, and an inorganic anion exchanger, such as hydrocalumite. The cement additive inhibits the alkali-aggregate reaction and the corrosion of reinforcing steel, thereby protecting concrete constructions from deterioration.

Cement-additive for inhibiting concrete-deterioration

A transistor is formed on a bonded SOI substrate. A collector electrode is connected to the peripheral sides of the collector areas on the insulator. A first insulator of isolation is formed on the peripheral side of the collector electrode. A base electrode is connected to a base area on the first insulator of isolation. Second insulators of isolation are formed on the peripheral side of a base electrode, and emitter electrode is connected to an emitter area by the second insulators of isolation. The connections between the collector electrode and the collector areas, between the base electrode and the base area, and between the emitter electrode and the emitter area are made under the emitter electrode, so the occupation area is small.

A semiconductor device has an electrically insulating substrate and a semiconductor layer formed on the insulating substrate. A plurality of semiconductor regions are defined so as to be joined to each other to form at least two homojunctions in the semiconductor layer. A lead conductor for one of the semiconductor regions which is required to have a small thickness has a specific structure such that the lead conductor is in contact with the one semiconductor region at the main surface of the semiconductor layer for electrical connection therebetween and extends over that portion of the semiconductor layer which contributes to definition of at least one of the semiconductor regions other than the first-mentioned one semiconductor region.

Semiconductor device for SOI structure having lead conductor suitable

An impurity diffusion method which can control a surface atomic concentration from a low to a high surface atomic concentration with a good uniformity is provided. Natural oxide is removed from the surface of a semiconductor substrate with a deoxidizing atmosphere gas as a diffusion atmosphere gas in advance, and then an impurity gas is passed thereto, while passing the deoxidizing atmosphere gas thereto, thereby conducting the diffusion. Flow rate or concentration of impurity of the impurity gas is so set that the impurity atomic concentration of the diffusion layer can be controlled by the flow rate or the concentration of impurity of the impurity gas. The impurity atomic concentration of the diffusion layer can be controlled by adjusting the flow rate or concentration of impurity of the impurity gas, and a diffusion layer having a low impurity atomic concentration can be formed. A shallow junction having a depth of not more than 50 nm can be formed.

Impurity diffusion method

A first region of a first conductivity type is formed in the surface of a semiconductor body, and second and third regions of a second conductivity type are formed on and under, respectively, of the first region. An electrode region formed on a first insulating film formed on the semiconductor body is connected electrically to the first region. The electrode region is defined as having an elongated first part an upper surface of which is connected to an electrode, and having a second, different part which has a substantially constant width and which width is substantially equal to the thickness of the first portion of the electrode region. A metal silicide film is formed over the upper surface of the first portion of the electrode region. The first, second and third regions can be base, emitter and collector regions, respectively, of a bipolar transistor formed in an island region of an epitaxially grown layer on a semiconductor substrate.

A vertical bipolar transistor arrangement in which the distance between the emitter and the isolation region is kept within a range determined by the sum of emitter depth and base width (i.e., the thickness of the base in the depth direction). This keeps the carriers given by the emitter from getting trapped inside, thereby preventing the cut-off frequency from dropping.

Semiconductor bipolar transistor with concentric regions

A semiconductor device including a polycrystalline silicone resistor which has a resistance of 40 k.OMEGA.-800 k.OMEGA. and which is formed by a polycrystalline silicon film having a specific resistivity of 0.01 .OMEGA..cm-0.1 .OMEGA..cm. The resistor having the above resistance, which has previously been difficult to fabricate, can be fabricated with a high accuracy, so it is very useful for several kinds of semiconductor integrated circuits such as bipolar memory.

Polycrystalline silicon resistor for use in a semiconductor integrated

The disclosure includes feeding a current I.sub.R to only BIT lines selected, or feeding current I.sub.R transiently to only the BIT lines switched from unselected to selected states; and a sense amplifier for detecting the difference between the currents flowing in selected BIT lines to read out stored information, wherein current I.sub.R and cell current I.sub.cell have a relation of I.sub.R &gt;I.sub.cell. The BiC MOS memory has high speed, low power and high integration density. Diodes are provided between the memory cell and the BIT lines.

Semiconductor cell memory with current sensing

Growing community of inventors

Tanashi, Japan

Tohru Nakamura