Nec Corporation

Photonics Electronics Technology Research Association

Renesas Electronics Corporation

Tohru Mogami

Tsuyoshi Horikawa

Keizo Kinoshita

Tatsuya Usami

Yoshiaki Yamamoto

Keiji Sakamoto

Toru Tatsumi

Shinichi Watanuki

Hitoshi Wakabayashi

Toyoji Yamamoto

Hiroyuki Nakamura

Tadahiko Sugibayashi

Koji Watanabe

Takashi Ishigami

Junichi Fujikata

Hisashi Takemura

Tadahiko Horiuchi

Risho Koh

Atsushi Ogura

Koichiro Okumura

Nobuyuki Ikarashi

Yukishige Saito

Akira Mitsuiki

Mitsuhiro Togo

Yukinori Ochiai

Atsuro Inada

Kazutoshi Shiba

Haruhiko Ono

Shigeharu Yamagami

Mitsuru Narihiro

Kohichi Arai

Jong-Wook Lee

Shigekazu Okumura

Takemitsu Kunio

Provided is an optical device in which an Si cap layer is provided on a Ge layer, and which is capable of effectively reducing dark current, while having a good effect on prevention of production line contamination by Ge. One embodiment of the optical device according to the present invention is provided with: a semiconductor layer which contains Ge and has a (001) surface and a facet surface between the (001) surface and a (110) surface; and a cap layer which is formed from Si, and which is formed on the (001) surface and the facet surface of the semiconductor layer. The ratio of the film thickness of the cap layer on the facet surface to the film thickness of the cap layer on the (001) surface is 0.4 or more; and the film thickness of the cap layer on the (001) surface is from 9 nm to 30 nm (inclusive).

Optical device

Provided is an optical waveguide circuit avoiding the difficulty of the property compensation based on temperature control, compensated with respect to the property variations due to fabrication error, particularly paid attention in a silicon waveguide, and being low in power consumption and high in performances. The optical waveguide circuit includes a silicon (Si) substrate, a buried oxide film (BOX) layer formed on the Si substrate, and an SOI (Silicon on Insulator) layer, formed on the BOX layer, including an optical element utilizing the SOI layer as a main optical transmission medium. At least part of a waveguide of the optical element includes uniformly distributed and thermally unstable crystal defects.

Optical waveguide circuit and method of fabricating same

A semiconductor device is provided with an insulating layer formed on a base substrate, an optical waveguide composed of a semiconductor layer formed on the insulating layer, and an insulating film formed along an upper surface of the insulating layer and a front surface of the optical waveguide. A peripheral edge portion of a lower surface of the optical waveguide is separated from the insulating layer, and the insulating film is buried between the peripheral edge portion and the insulating layer.

Semiconductor device and method for manufacturing the same

When an optical waveguide is formed, an area of an opening of a resist mask is equal to an area of a semiconductor layer for a dummy pattern exposed from the resist mask, and the semiconductor layer for the dummy pattern exposed from the resist mask has a uniform thickness in a region in which the dummy pattern is formed. As a result, an effective pattern density does not change in etching the semiconductor layer for the dummy pattern, and accordingly, it is possible to form a rib-shaped optical waveguide having desired dimensions and a desired shape.

A performance of a semiconductor device is improved. In a method of manufacturing a semiconductor device, a first semiconductor portion and a second semiconductor portion made of silicon are formed on a base body via an insulation layer, and a third semiconductor portion including a semiconductor layer made of germanium is formed on the second semiconductor portion. Next, an insulation film is formed above the first semiconductor portion, an opening portion reaching the first semiconductor portion from an upper surface of the insulation film is formed, and a metal silicide layer is formed on a part of an upper surface of the first semiconductor portion exposed to the opening portion.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a semiconductor layer formed on an insulator, a gate insulating film formed on the semiconductor layer, a gate electrode formed on the gate insulating film and extending in a first direction, source/drain regions formed in the semiconductor layer on both sides of the gate electrode, a body contact region in the semiconductor layer, a partial isolating region in which a field insulating film thicker than the gate insulating film intervenes between the semiconductor layer and an extending portion of the gate electrode, and a full isolating region in which the semiconductor layer on the insulator is removed. The full isolating region is formed to be in contact with at least a part of a side parallel to the first direction of the source/drain regions.

SOI MOSFET

A semiconductor integrated circuit device has a plurality of basic cells. The basic cells are placed in a matrix form, and are formed on a semiconductor substrate. Each of the basic cells includes a wire selection portion and a logic gate portion. The logic gate portion has a MOS transistor. The wire selection portion has a thin-film transistor serving as a transfer gate. The wire selection portion is placed over the logic gate portion via an interlayer insulating film.

Semiconductor integrated circuit and semiconductor integrated circuit device

A MIS transistor has a gate insulating film made of silicon oxynitride and having a specific dielectric constant which is larger than the expected specific dielectric constant calculated based on a weighted average of the specific dielectric constants based on the weight ratio of the silicon oxide and the silicon nitride contained in the silicon oxynitride film. The gate insulating film having a smaller thickness prevents impurities in the overlying gate electrode from penetrating through the gate insulating film to degrade the silicon substrate.

Semiconductor device including a MIS transistor

In a method for manufacturing a salicide MOS device, a gate insulating layer and a polycrystalline silicon gate electrode layer are formed on a monocrystalline silicon substrate. A sidewall insulating layer is formed on a sidewall of the gate electrode layer, and impurities are introduced into the substrate with a mask of the sidewall insulating layer and the gate electrode layer, thus forming impurity diffusion regions in the substrate. Then, an upper portion of the gate electrode layer is etched out. Finally, a metal layer is formed on the entire surface, and a heating operation is carried out, so that metal silicide layers are formed on upper portions of the gate electrodes and the impurity diffusion regions. In an alternative embodiment, the gate further comprises an intervening metal nitride layer.

Method for manufacturing salicide semiconductor device

A method of producing a semiconductor device having a refractory metal silicide film includes the steps of implanting ions such as silicon into an active region such as drain/source region to form a damage portion therein, depositing a refractory metal on the damage portion, and annealing to form the refractory metal silicide layer. This silicide layer is formed by the refractory metal being reacted with silicon in the damage portion of the active region.

Method of fabricating semiconductor device having refractory metal

In a method of manufacturing a semiconductor device, a step (d) of forming metal silicide films (20) on source and drain regions (17, 18) and on gate electrodes (71, 81) comprises selectively depositing silicon thin films (19) on the source and drain regions and the gate electrodes, the silicon thin films having impurity concentration less than 10.sup.19 cm.sup.-3 ; amorphizing the silicon thin films, the gate electrodes, and a silicon semiconductor substrate (11) by ion implantation; depositing a metal film on the silicon thin films, on the gate electrodes, and on the silicon semiconductor substrate; performing heat treatment of the metal film to form the metal silicide films (20) on the source and drain regions and the gate electrodes; and removing unreacted metal films (21) remaining on insulating films (16-1, 16-2). Preferably, the selectively depositing step may be performed by a chemical vapor deposition process of a reaction rate-determining mode by using disilane gas or silane gas.

Method of manufacturing a semiconducter device capable of easily forming

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Tokyo, Japan

Tohru Mogami