Fujitsu Corporation

Tohru Mizutani

Hiromi Nanba

Atsushi Matsuda

Masato Takeyabu

Makoto Ikeshita

Masashi Okubo

Kenichi Minobe

Yoshinori Yoshikawa

Atsushi Hitaka

An evaluation circuitrepeats processing in which an output VD thereof is reset, there is obtained repeatedly given times a difference between sampled output voltages Vo of a replica circuitR when respective times tand thave elapsed after a voltage Vi is step-inputted to the replica circuitR, and the differences are successively summed. A comparator circuitcompares a difference cumulation voltage VD with a reference voltage VS. A bias adjustment circuitsteps up the bias currents of the replica circuitR and an adjusted circuitat every this given times if VD&#x3e;VS, and ceases the adjustment if VD&#x3c;VS.

Low power circuit with proper slew rate by automatic adjustment of bias current

An integrated circuit includes an analog signal output unit which converts a digital output signal into at least one analog output signal, and outputs the at least one analog output signal, an analog signal input unit which converts at least one analog input signal received from an exterior into a digital input signal, a switch circuit which provides at least one signal path through which the at least one analog output signal is supplied from the analog signal output unit to the analog signal input unit as the at least one analog input signal, and an offset adjustment control circuit which supplies an output offset from the analog signal output unit to the analog signal input unit via the at least one signal path so as to detect the digital input signal inclusive of the output offset and an input offset, and cancels offsets of the analog signal output unit and the analog signal input unit in response to the output offset and the input offset obtained from the detected digital input signal.

Digital-analog-conversion circuit having function of automatic offset adjustment

First and second switches are connected at each node between adjacent resistors in a resistor row and at the end of the resistor row. A predetermined number of first switches are grouped together and short-circuited to obtain a plurality of first switch groups, and a predetermined number of second switches are grouped together and short-circuited to obtain a plurality of second switch groups. The first and second switch groups are connected to output terminals via output switches. The first and second switches are ON/OFF controlled such that only one switch in the first and second switch groups is connected to the resistance row.

Digital-analog converter

An evaluation circuit repeats processing in which an output VD thereof is reset, there is obtained repeatedly given times a difference between sampled output voltages Vo of a replica circuit R when respective times t and t have elapsed after a voltage Vi is step-inputted to the replica circuit R, and the differences are successively summed. A comparator circuit compares a difference cumulation voltage VD with a reference voltage VS. A bias adjustment circuit steps up the bias currents of the replica circuit R and an adjusted circuit at every this given times if VD>VS, and ceases the adjustment if VD<VS.

Growing community of inventors

Kawasaki, Japan

Tohru Mizutani