Hitachi, Ltd.

Tohru Kobayashi

Toshio Yamada

Masato Hamamoto

Atsushi Shimizu

Satoru Isomura

Hiromasa Katoh

Mitsuo Usami

Hiroyuki Itoh

Mikinori Kawaji

Yuko Ito

Takeo Yamada

Nobuo Owada

Tatsuya Kimura

Noboru Shiozawa

Kaoru Koyu

Kazuyoshi Satoh

Kazuo Tanaka

Keiichi Higeta

Akira Masaki

Kunihiko Yamaguchi

Tatsuya Saitoh

Kengo Miyazawa

Kaoru Oogaya

Hirotaka Nishizawa

Kazuo Nakamura

Hiroki Yamashita

Masayoshi Yagyu

Osamu Kasahara

Keiichirou Nakanishi

Hiroyuki Akimori

Takahisa Nitta

Shunji Sasabe

Yasuo Satoh

Masaru Osanai

Yoshuhiro Fujimura

A memory portion and a logic circuit portion of a semiconductor device are formed on a single semiconductor substrate in which a first logic circuit block and a second logic circuit block are formed in different areas and the second logic circuit is located between a pair of memory blocks. Data stored in the pair of memory blocks are transmitted to the second logic circuit block for processing via a memory peripheral circuit. A result of the data processing is transmitted to the first logic circuit block or an external device via an input/output circuit provided in the second logic circuit block. A clock signal entered at the center portion of the semiconductor chip is supplied to a plurality of first state clock distributing circuits equidistantly disposed from the center portion and then to a plurality of second stage clock distributing circuits at least equidistantly disposed from each of the first state clock distributing circuits. Next, the clock signal is supplied to a plurality of third state clock distributing circuits equidistantly disposed from each of the second stage clock distributing circuits and then supplied to a plurality of final stage clock distributing circuits equidistantly disposed from each of the third stage clock distributing circuits. From these final stage clock distributing circuits, the clock signal is supplied to an area in whose units an internal gate array and a RAM macro cell or a logic macro cell are made replaceable with each other.

Semiconductor integrated circuit device and method of manufacturing the

A semiconductor integrated circuit device having a memory portion and a logic circuit portion formed with a same semiconductor substrate comprising a first logic circuit block, a second logic circuit block disposed in an area different from an area in which the first logic circuit block is disposed, and a pair of memory blocks oppositely disposed so that the second logic circuit block comes in between. Data stored in the pair of memory blocks are transmitted to the second logic circuit block for processing via a memory peripheral circuit provided on the second logic circuit block. A result of the data processing is transmitted to the first logic circuit block or an external device via an input/output circuit provided in the second logic circuit block.

Semiconductor integrated circuit device with interleaved memory and

A power source wiring supplies power to individual electronic circuits constituting an electronic circuit device. Load circuits are connected to the power source wiring within the range of an arrival time of a voltage noise occurring in the power source wiring in a time of about a half of a pulse width of a noise current at the time of the operation of the electronic circuit. Each of these load circuits includes a series circuit of a resistance and a capacitance.

Electronic circuit device having a series connection of resistor and

A semiconductor IC device has an input/output circuit and an internal logic circuit connected with the input/output circuit formed in a main surface of a semiconductor substrate of a generally rectangular shape. The input/output circuit is divided into at least two input/output circuit blocks in such a manner that edges of the logic circuit blocks defined by the division on the main surface of the substrate extend in a direction substantially parallel with a pair of opposite sides of the substrate. The internal logic circuit is divided into at least three logic circuit blocks in such a manner that edges of the logic circuit blocks defined by the division on the main surface of the substrate extend in the above-mentioned direction. Each of the input/output circuit blocks is sandwiched by and electrically connected with adjacently arranged two of the logic circuit blocks.

Integrated circuit having alternate rows of logic cells and I/O cells

Herein disclosed is a chip-carrier type semiconductor device adopting the MCC structure, in which a semiconductor pellet is mounted on the surface of the base substrate and in which mounting terminals to be connected with external terminals of the semiconductor pellet are mounted on the rear surface of the base substrate. In order to effect a test such as screening easily and inexpensively even if the mounting terminals are multiplied or miniaturized, the chip-carrier type semiconductor device adopting the MCC structure is equipped on the side surfaces of the base substrate with auxiliary terminals to be electrically connected with a plurality of external terminals which are arrayed on an element formed main surface of the semiconductor pellet.

Semiconductor device and semiconductor module having auxiliary high

In accordance with one aspect of the invention, a semiconductor integrated circuit is provided wherein an input circuit is formed by a phase split circuit having a bipolar transistor which outputs an inverted output from the collector and a non-inverted output from the emitter. The emitter follower output circuit is driven by an inverted output of the phase split circuit. Meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit. As a second aspect of the invention, a logic circuit is formed of a logic portion and an output portion. The output portion includes an emitter follower output transistor receiving an output signal generated by the logic portion and an active pull-down transistor receiving at its base a signal supplied thereto through a capacitance element. The signal received by the active pull-down transistor has a phase reverse to that of the input signal supplied to the base of said output transistor. Between the base and emitter of the active pull-down transistor, there is disposed a bias circuit formed of a transistor receiving at its base a predetermined bias voltage and an emitter resistor. Further, between a junction point of the emitter follower output transistor and the active pull-down transistor and the emitter of the transistor as a constituent of the bias circuit, there is disposed a capacitance element for feeding back the output signal.

Semiconductor integrated circuit device with a plurality of logic

A multi-layered structure of wirings on a semiconductor substrate has been employed in conjunction with the increase in the integration density of semiconductor integrated circuit devices. In the invention, dummy patterns made of the same material as an Al wiring layer for compensating for any step or level gradation are disposed in the regions below bump electrodes and in the proximity thereof in order to reduce any defects inherent to a multi-layered structure that occur in CCB bump electrodes formed on the multi-layered wirings and at pads as the base layer of the former.

Semiconductor integrated circuit device in which a semiconductor chip is

Flip-flops are disposed corresponding to input circuits or output circuits of an integrated logic circuit so as to be cascaded to configure a shift register for a test and to enable a parallel transfer of data between each flip-flop and a corresponding input or output circuit. As a result, without connecting the probe to all terminals of the LSI, test signals can be supplied from some terminals via all input circuits to an internal circuit so as to conduct a diagnosis.

Integrated logic circuit

Disclosed is a semiconductor integrated circuit device adopting a gate array scheme, having a plurality of layers of wiring formed by a Design Automation system. The device according to the present invention includes a semiconductor substrate having basic cell forming regions, the basic cell forming regions being spaced from each other with wiring channel regions between adjacent basic cell forming regions. The wiring includes at least first-layer wiring lines arranged overlying the wiring channel regions; second-layer wiring lines overlying both the basic cell forming regions and the wiring channel regions; and third-layer wiring lines overlying both the basic cell forming regions and the wiring channel regions. The first-, second- and third-layer wiring lines respectively extend in first, second and third directions, the second direction being different from the first direction. The wiring pitches of the second-layer wiring lines and the third-layer wiring lines are set substantially equal to or smaller than the wiring pitch of th first-layer wiring lines. As a further aspect of the present invention, the ratio of wiring pitch of third-layer wiring lines to first-layer wiring lines can be 0.5, 1.0, 1.5 or 2.0. In addition, insulator films on which are formed the wiring lines are respectively subjected to flattening processes in order to flatten their upper surfaces, prior to providing the wiring lines thereon.

Integrated logic circuit having plural input cells and flip-flop and

A multi-layered structure of wirings on a semiconductor substrate has been employed in conjuction with the increase in the integration density of semiconductor integrated circuit devices. In the invention, dummy patterns made of the same material as an Al wiring layer for compensating for any step or level gradation are disposed in the regions below bump electrodes and in the proximity thereof in order to reduce any defects inherent to a multi-layered structure that occur in CCB bump electrodes formed on the multi-layered wirings and at pads as the base layer of the former.

A MIS capacitor to be implemented in a semiconductor device employing various or predetermined circuits, has a dielectric side electrode which is in contact with a buried layer provided on a semiconductor substrate through a dielectric film and a buried layer-side electrode connected to the buried layer. The buried layer-side electrode of the MIS capacitor is connected to a low-impedance side of the circuit employed therewith. This structure, when connected as such, is capable of reducing the influence of noise attributed to an .alpha.-ray and thereby operating the circuit stably. The semiconductor device using a MIS capacitor invention is adaptable to an emitter follower circuit and various logic circuits for preventing malfunction resulting from .alpha.-ray radiation.

Semiconductor device using MIS capacitor

A semiconductor integrated circuit wherein an input circuit is formed by a phase split circuit consisting of a bipolar transistor which outputs an inverted output from the collector and non-inverted output from the emitter, the emitter follower output circuit is driven by an inverted output of the phase split circuit, meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit.

High speed TTL buffer circuit which is resistive to the influence of

In a gate array integrated circuit including a plurality of logic gate circuits having a wired-OR form, or the like, a first common combined wiring is provided for connecting the output side in such a manner that the output terminal of each logic gate circuit and a branch node corresponding thereto are in the proximity of one another. A terminal resistor is interposed between a first end of the first common combined wiring and a power source voltage or ground potential of the circuit, and the second end of the first common combined wiring is coupled to a second common combined wiring connecting the input terminals of the logic gate circuits on the input side.

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Iruma, Japan

Tohru Kobayashi