Fujitsu Corporation

Fujitsu Semiconductor Limited

Tohru Anezaki

Taiji Ema

Junichi Mitani

The semiconductor device includes a first conductor formed over a semiconductor substrate; a first insulator formed over the first conductor; a second insulator formed over the first insulator, the second insulator having an etching characteristic different from an etching characteristic of the first insulator; a second conductor formed on the second insulator, the second conductor being in contact with the second insulator; a third insulator formed over the second conductor, the third insulator having an etching characteristic different from the etching characteristic of the second insulator; a first contact hole formed through the third insulator and the second conductor, the first contact hole reaching the second insulator; a third conductor formed in the first contact hole, wherein a side wall of the third conductor is electrically connected to a side wall of the second conductor; a second contact hole formed through the third insulator and the first insulator, the second contact hole reaching the first conductor; and a fourth conductor formed in the second contact hole, wherein the fourth conductor is electrically connected to the first conductor.

Semiconductor device

The method of manufacturing a semiconductor device includes a first conductor over a semiconductor substrate; forming a first insulator over the first conductor; forming a second insulator, having an etching characteristic different from an etching characteristic of the first insulator, over the first insulator; forming a second conductor on the second insulator, the second conductor being in contact with the second insulator; forming a third insulator, having an etching characteristic different from the etching characteristic of the second insulator, over the second conductor; forming a first contact hole though the third insulator and the second conductor, the first contact hole exposing the second insulator; forming a second contact hole through the third insulator and the first insulator, the second contact hole exposing the first conductor; forming a third conductor in the first contact hole, wherein a side wall of the third conductor is electrically connected to a side wall of the second conductor; forming a fourth conductor in the second contact hole, wherein the fourth conductor is electrically connected to the first conductor.

Method of manufacturing semiconductor device

The semiconductor storage device comprises memory cell transistors formed on a semiconductor substrate; first insulation filmscovering the top surfaces and the side surfaces of gate electrodesof the memory cell transistors; through-holesopened on first diffused layers; a second insulation filmwith through-holesopened on first diffused layersand through-holesopened on second diffused layersformed in; capacitors formed on the inside walls and the bottoms of the through-holesand including capacitor storage electrodes, connected to the first diffused layers; capacitor dielectric filmscovering the capacitor storage electrodes, and capacitor-opposed electrodescovering at least a part of the capacitor dielectric films; and, contact conducting filmsformed on the inside walls and bottoms of the through-holes, and connected to the second diffused layers. This structure of the semiconductor storage device makes it unnecessary to secure an alignment allowance for alignment of the through-holesopened on the first diffused layerand the through-holesopened on the second diffused layerwith the gate electrode, which permits the semiconductor storage device to have a small memory cell area.

Semiconductor storage device and method for fabricating the same

Semiconductor storage device

A semiconductor device includes a semiconductor substrate; an insulating laminate formed over the semiconductor substrate, and including a lower part and a higher part formed over the lower part; a first conductor formed in the higher part of the insulating laminate, an insulator, having an etching characteristic different from the lower part and the higher part of the insulating laminate, formed between the lower part of the insulating laminate and the first conductor, a first contact hole formed through the higher part of the insulating laminate, penetrating inside peripheral edges of the first conductor, reaching the insulator; and a second conductor filled in the first contact hole and electrically connected to the first conductor at its side wall exposed in the first contact hole.

A semiconductor device with a self-aligned opening and a method for fabricating the same, the semiconductor device including a first conductor pattern formed over a semiconductor substrate; a first insulation film formed over the first conductor pattern; a second insulation firm formed over the first insulation film, the second insulation film having a substantially flat surface and having etching characteristics different from those of the first insulation film; a third insulation film formed over the second insulation film, the third insulation film having etching characteristics different from those of the second insulation film; a fourth insulation film formed over the third insulation film, the fourth insulation film having etching characteristics different from those of the third insulation film; an opening formed in the fourth insulation film, the third insulation film, the second insulation film, and the first insulation film, the opening being self-aligned with the first conductor pattern, a second conductor pattern formed in the opening.

Semiconductor storage device with self-aligned opening and method for fabricating the same

The semiconductor device includes a MOSFET including a pair of impurity diffused regions formed on both sides of a gate formed on a semiconductor substrate; an insulation film covering a top of the MOSFET and having a through-hole opened on one of the impurity diffused regions formed in; and a capacitor formed at at least a part of an inside of the through-hole, the through-hole having a larger diameter inside than at a surface thereof or having a larger diameter at an intermediate part between the surface thereof and a bottom thereof than the surface and the bottom thereof.

Semiconductor device and method for fabricating the same

The semiconductor storage device comprises memory cell transistors formed on a semiconductor substrate ; first insulation films covering the top surfaces and the side surfaces of gate electrodes of the memory cell transistors; through-holes opened on first diffused layers ; a second insulation film with through-holes opened on first diffused layers and through-holes opened on second diffused layers formed in; capacitors formed on the inside walls and the bottoms of the though-holes and including capacitor storage electrodes , connected to the first diffused layers ; capacitor dielectric films covering the capacitor storage electrodes , and capacitor-opposed electrodes covering at least a part of the capacitor dielectric films ; and, contact conducting films formed on the inside walls and bottoms of the through-holes , and connected to the second diffused layers. This structure of the semiconductor storage device makes it unnecessary to secure an alignment allowance for alignment of the through-holes opened on the first diffused layer and the though-holes opened on the second diffused layer with the gate electrode , which permits the semiconductor storage device to have a small memory cell area.

Method for fabricating semiconductor storage device

The semiconductor storage device comprises memory cell transistors formed on a semiconductor substrate 10; first insulation films 42 covering the top surfaces and the side surfaces of gate electrodes 20 of the memory cell transistors; through-holes 40 opened on first diffused layers 24; a second insulation film 36 with through-holes 40 opened on first diffused layers 24 and through-holes 38 opened on second diffused layers 26 formed in; capacitors formed on the inside walls and the bottoms of the through-holes 40 and including capacitor storage electrodes 46, connected to the first diffused layers 24; capacitor dielectric films 48 covering the capacitor storage electrodes 46, and capacitor-opposed electrodes 54 covering at least a part of the capacitor dielectric films 48; and, contact conducting films 44 formed on the inside walls and bottoms of the through-holes 38, and connected to the second diffused layers. This structure of the semiconductor storage device makes it unnecessary to secure an alignment allowance for alignment of the through-holes 40 opened on the first diffused layer 24 and the through-holes 38 opened on the second diffused layer 26 with the gate electrode 20, which permits the semiconductor storage device to have a small memory cell area.

Growing community of inventors

Kawasaki, Japan

Tohru Anezaki