International Business Machines Corporation

Todd Williams

Roderick M West

Steven William Tomashot

Robert Tamlyn

Satish Gupta

Nathan R Hiltebeitel

Randall L Henderson

John E Gersbach

Roderick Michael West

Roy Childs Flaker

Adrian C Gay

Timothy J Ebbers

Gregory J Schroer

Matthew Damien Bates

An integrated memory structure, and associated processing method, is coupled to receive address data and control data. The memory structure includes a composite memory array having a first array portion and a second array portion which are separately addressable. The first array portion is accessed using at least some of the address data as a first address signal and the second array portion is addressed using at least some of the control data also as a second address signal. The memory structure is presented herein by way of example for a serial palette digital-to-analog (SPD) device, and incorporates indirect color mode, direct color mode, overlay color mode and cursor color mode processing in a single macro. When in direct color mode, access to the memory array is disabled and address data is transferred directly to an output of the memory structure as data out.

Memory structure with multiple integrated memory array portions

A filter network is presented for a phase-locked loop (PLL) circuit having a voltage controlled oscillator (VCO) with a control input and a bias input. The filter network includes a conventional filter circuit that provides a 'pole' and a 'zero' to the transfer function of the PLL circuit. The conventional filter circuit is coupled between the control input of the VCO and ground. An additional filter circuit is also coupled to the control input of the VCO, and to a bias input of the VCO. This additional filter circuit provides at least one additional 'zero' to the PLL transfer function to extend the frequency range of the PLL circuit without impairing circuit stability. A transconductance amplifier is preferably employed within the additional filter circuit to facilitate tailoring of the open loop gain of the filter/oscillator circuitry.

Filter network for phase-locked loop circuit

In a memory addressable by row and by column and operable in page mode whereby multiple column cycles are performed within a single row cycle, an arrangement is provided for stepping the row address for selected column cycles whereby sustained page mode operation can be provided throughout memory address space. Preferably, stepping occurs in response to a row change signal supplied when a column address strobe becomes active and the direction of stepping is determined by a mode signal supplied when a row address strobe becomes active. Memory segmentation is employed to facilitate simultaneous activation and restoring of multiple rows.

Memory with page mode

A Video Random Access Memory device wherein full and efficient use of a serial access memory portion provides a simple and efficient means of avoiding Mid-Line Reloads. Selected parts of two different rows in a random access memory portion are transferred simultaneously to the serial access memory portion via addressable transfer gates under the control of address/control logic.

Video Random Access Memory serial port access

Video random access memory serial port access

An implementation of a serial access memory register that facilitates the selecting from two alternate frame buffers on a per pixel basis. The frame buffers are each stored in a portion of a row in a single video RAM. Following data transfer to the serial access memory register, data from each of the two frame buffers is available. A double buffer select signal controls the selection of which half of the serial access memory register will put data on the output bus for each serial clock signal. The serial clock increments the address pointers in both halves of the serial access memory port simultaneously.

Video RAM double buffer select control

An implementation of a serial access memory register facility which allows the external selection of the portion of the SAM to be scanned out. A control signal is provided which causes the reloading of serial access memory address counter causing the reloading of serial access memory address counter causing the serial scanning to shift from one to another of the serial access memory registers. The result is an ability to select a stopping point when scanning out of the serial access memory. Thus, the present invention implements the ability in a video random access memory to specify both the starting and ending points of the data to be scanned out of the serial access memory. The preferred embodiment replaces the QSF status pin with a control pin to preserve the packaging configuration of standard VRAMs.

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Westford, VT, United States of America

Todd Williams