Emc IP Holding Company LLC

Mellanox Technologies, Ltd.

Todd Wilde

Bruce Alexander Wilford

Richard Van Gaasbeck

Vikram Venkataraghavan

Mark Himelstein

Vishwas Durai

Rick Carlson

Blair Barnett

Kevin J Rowett

Samir Rajadnya

Karthik Ramachandran

Michael Kagan

Diego Crupnicoff

Richard Leigh Graham

Michael Nishimoto

James Yarbrough

According to one embodiment, a data processing system includes a plurality of processing units, each processing unit having one or more processor cores. The system further includes a plurality of memory roots, each memory root being associated with one of the processing units. Each memory root includes one or more branches and a plurality of memory leaves to store data. Each of the branches is associated with one or more of the memory leaves and to provide access to the data stored therein. The system further includes a memory fabric coupled to each of the branches of each memory root to allow each branch to access data stored in any of the memory leaves associated with any one of remaining branches.

Exabyte-scale data processing system

In general, embodiments of the technology relate to a method and system for storing and reading data from persistent storage. More specifically, embodiments of the technology relate to a method and system for storing data in persistent storage, where the data written to the persistent storage is not immediately accessible in the persistent storage (i.e., during the inaccessibility period). In such instances, embodiments of the technology provide a method and system to enable the storage system to service read requests for the data using a primary cache entry table (PCET) and an overflow table.

Method and system for writing data to and read data from persistent storage

Data processing system with a scalable architecture over ethernet

According to one embodiment, a data processing system includes a plurality of processors, each of the processors being coupled to each of remaining processors via a processor interconnect, a plurality of memory controllers, each memory controller corresponding to one of the processors, a plurality of memory targets, each memory target includes one or more branches and a plurality of memory leaves for storing data, and an Ethernet switch fabric coupled to the memory controllers and the memory targets. When a first of the memory controllers writes data to a first of the memory leaves, the first memory controller sends a cache coherence message to remaining ones of the memory controllers to indicate that the data stored in the first memory leaf has been updated, such that any of the remaining memory controllers can update its cache by fetching the data from the first memory leaf.

Non-uniform memory access (NUMA) mechanism for accessing memory with cache coherence

According to one embodiment, a data processing system includes a plurality of central processing unit (CPU) subsystems, each CPU subsystem having a plurality of CPUs and a plurality of memory controllers, each memory controller corresponding to one of the CPUs, a plurality of memory complexes, each memory complex being associated with one of the CPU subsystems, wherein each memory complex comprises one or more branches, a plurality of memory leaves to store data, wherein each of the branches is coupled to one or more of the memory leaves and to provide access to the data stored in the memory leaves, and a replication interface to automatically replicate data received from one of the CPU subsystems to another one of the memory complexes, wherein the received data is to be stored in one of the memory leaves.

Flash memory complex with a replication interface to replicate data to another flash memory complex of a data processing system

A page virtualization table (PVT) and one or more block virtualization tables (BVTs) are maintained. The PVT includes PVT entries, each mapping a logical page number (LPN) to a virtual page number (VPN). Each BVT includes BVT entries, each mapping a virtual block number (VBN) to a physical block number (PBN). A request is received for accessing data stored in one of flash memory devices, the request including a first LPN. A search is performed in the PVT based on the first LPN to locate a first PVT entry to obtain a first VPN from the first PVT entry. A search is performed in a first BVT to locate a first BVT entry based on the VPN to obtain a first PBN from the first BVT entry. An input and output (IO) request is issued based on the first PBN to a flash controller associated with a first flash memory device that stores data corresponding to the first PBN.

Software-implemented flash translation layer policies in a data processing system

One or more virtual functions are exposed via a shared communication interface. Memory across said virtual functions is shared to provide a fixed number of I/O buffers shared across said virtual functions. For each of said one or more virtual functions, storing a corresponding map table configured to store a mapping data that maps a logical block address of the virtual function to a corresponding allocated one of said fixed number of I/O buffers based at least in part on a current state of a state machine.

Virtual I/O queuing

A target channel adapter in configured to generate and maintain for each of a plurality of endpoints a corresponding set of metadata. Each endpoint is associated with a corresponding set of storage modules and the set of metadata corresponding to each endpoint is associated with accessing storage locations in the set of storage modules associated with that endpoint. The target channel adapter is configured to use the set of metadata to provide to a remote client associated with a media access controller access to data stored in one or more of said storage modules.

Virtualized target channel adapter

One or more virtual functions is exposed via a shared communication interface. A plurality of I/O buffers shared across said virtual functions are provided. For each of said one or more virtual functions, a corresponding submission queue comprising one or more virtual submission queue entries (SQEs) is used, wherein a memory access device is configured to: receive data pushed to the memory access device by a client host system, store the data in an allocated one of the I/O buffers, receive a submission queue entry (SQE) that invokes one of said virtual functions with respect to the data, and use a corresponding one of the plurality of logic circuits that is associated with the invoked virtual function to perform the virtual function with respect to the data as stored in the allocated I/O buffer.

Host to device I/O flow

A network interface device for a host computer includes a network interface, configured to transmit and receive data packets to and from a network. Packet processing logic transfers data to and from the data packets transmitted and received via the network interface by direct memory access (DMA) from and to a system memory of the host computer. A memory controller includes a first memory interface configured to be connected to the system memory and a second memory interface, configured to be connected to a host complex of the host computer. Switching logic alternately couples the first memory interface to the packet processing logic in a DMA configuration and to the second memory interface in a pass-through configuration.

Growing community of inventors

Palo Alto, CA, United States of America

Todd Wilde