Seagate Technology Incorporated

Todd Ray Strope

John Edward Moon

Stanton MacDonough Keeler

Robert Dale Murphy

Paul Francis Kusbel

Preston Donald Sellers

In a particular embodiment, a system includes a controller adapted to determine a data transfer rate associated with at least one data stream to be written to a storage media and to selectively activate at least one of a first memory and a second memory based on the data transfer rate to record the at least one data stream.

Storage device and controller to selectively activate a storage media

The present disclosure is directed to systems and methods of matching data rates. In a particular embodiment, a device includes a first data bus and a controller having a first output coupled to the first data bus to provide data to the first data bus. The device also includes a first memory of a first type coupled to the first data bus. The first memory may have a first input to receive data from the controller via the first data bus. The device also includes logic coupled to the first data bus. The logic may have a second input coupled to the first data bus to receive data from the controller via the first data bus. The device may also include a second data bus coupled to the logic. The logic may have a second output coupled to the second data bus to provide data to the second data bus. The logic may also include a second memory of a second type coupled to the second data bus. The second memory may have a third input to selectively receive data from the logic via the second data bus. The logic may be adapted to receive data and select the first memory or the second memory to store data.

System and method of matching data rates

Methods of encoding data to and decoding data from flash memory devices are provided. User data having an unknown ratio of 1's to 0's is received. The user data is utilized in generating transformed data that has a predictable ratio of 1's to 0's. The transformed data is stored to flash memory. The transformed data is illustratively generate by either applying an 'exclusive or' function to the user data or by converting the user data into a number having a greater number of bits.

Encoding and decoding to reduce switching of flash memory transistors

This disclosure is related to systems and methods for storing data in multi-level cell solid state storage devices, such as Flash memory devices. In one example, a multi-level cell memory array has programmable pages, a first page having a first programming time, and a second page having a second programming time that is different than the first programming time. In one embodiment, the first programming time is faster than the second programming time. Further, a controller coupled to the multi-level cell memory array may be configured to select the first page to store the data when a priority level of a write operation indicates a first priority level and select the second page to store the data when the priority level indicates a second priority level.

Systems and methods for storing data in a multi-level cell solid state storage device

A data storage device includes a solid state data storage medium, a set of related data blocks and a controller. The set of related data blocks are non-contiguously stored on the data storage medium and have an original write sequence. The controller, responsive to a defragmentation request, maps the physical block addresses of the set of related data blocks to contiguous logical block addresses in the original write sequence while maintaining the non-contiguous physical block addresses of the set of related data blocks on the data storage medium.

Growing community of inventors

Longmont, CO, United States of America

Todd Ray Strope