Micron Technology Incorporated

Todd R Abbott

Jigish D Trivedi

Zhongze Wang

Chih-Chen Cho

Mike P Violette

Michael P Violette

Charles H Dennison

Homer M Manning

H Montgomery Manning

Kevin J Torek

Sandra Tagg

Chuck H Dennison

Amy Weatherly

Monte Manning

Shubneesh Batra

Mark Fischer

Raymond A Turi

Jigish D Trevidi

John D Trivedi

Garo Jacques Derderian

Jigish D Tirvedi

A photoresist processing method includes treating a substrate with a sulfur-containing substance. A positive-tone photoresist is applied on and in contact with the treated substrate. The method includes selectively exposing a portion of the photoresist to actinic energy and developing the photoresist to remove the exposed portion and to form a photoresist pattern on the substrate. The treating with a sulfur-containing substance reduces an amount of residual photoresist intended for removal compared to an amount of residual photoresist that remains without the treating.

Photoresist processing methods

A flash memory device wherein the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device density. The floating gate can also be elevated above the substrate a selected amount so as to achieve a desirable coupling between the substrate, the floating gate and the control gate comprising the flash cell.

Flash memory with recessed floating gate

DRAM cell arrays having a cell area of about 4Fcomprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is orthogonal to at least one of the vertical gate electrodes of the vertical transistors.

DRAM layout with vertical FETS and method of formation

DRAM cell arrays having a cell area of less than about 4Fcomprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is non-orthogonal to at least one of the vertical gate electrodes of the vertical transistors.

DRAM layout with vertical FETs and method of formation

DRAM cell arrays having a cell area of about 4 Fcomprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is orthogonal to at least one of the vertical gate electrodes of the vertical transistors.

DRAM cell arrays having a cell area of less than about 4 Fcomprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is non-orthogonal to at least one of the vertical gate electrodes of the vertical transistors.

DRAM memory cells having a feature size of less than about 4F2 include vertical surround gate transistors that are configured to reduce any short channel effect on the reduced size memory cells. In addition, the memory cells may advantageously include reduced resistance word line contacts and reduced resistance bit line contacts, which may increase a speed of the memory device due to the reduced resistance of the word line and bit line contacts.

DRAM including a vertical surround gate transistor

A flash memory device where the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device density. The floating gate can also be elevated above the substrate a selected amount so as to achieve a desirable coupling between the substrate, the floating gate and the control gate incorporating the flash cell.

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Boise, ID, United States of America

Todd R Abbott