National Semiconductor Corporation

Todd Patrick Thibeault

Sergei Drizlikh

Steven J Adler

Andre Paul Labonte

Thomas Francis

Scott David Ruby

Paul A Fearon

An isolation trench structure includes both a deep trench isolation (DTI) trench and a shallow trench isolation (STI) trench. The DTI trench can be formed by etching a deeper, narrower trench in a substrate and filling the deeper trench with one or more materials (such as an oxide). The STI trench can be formed by etching a shallower, wider trench in the substrate and filling the shallower trench with one or more materials (such as an oxide). The STI trench surrounds a portion of the DTI trench, such as by completely encircling an upper portion of the DTI trench. The DTI and STI trenches are filled during different operations, and the DTI and STI trenches can be filled with the same material(s) or with different material(s).

Apparatus and method for isolating integrated circuit components using deep trench isolation and shallow trench isolation

A system and method are disclosed for manufacturing an emitter structure in a complementary bipolar complementary metal oxide semiconductor (CBiCMOS) transistor manufacturing process. A protective layer is formed over an emitter layer in a transistor structure and lateral portions of the protective layer and the emitter layer are etched to form an emitter structure. An oxide layer is then deposited over the transistor structure and an etchback process is performed to remove portions of the oxide layer from the top of the protective layer. A source/drain implant process is then performed to implant an extrinsic base region of the transistor. The protective layer protects the emitter structure from the implant process. Then the protective layer is removed from the emitter structure.

System and method for manufacturing an emitter structure in a complementary bipolar CMOS transistor manufacturing process

In an inductor integration process, a high Q inductor is achieved by forming an AlCu inductor via prior to depositing the inductor dielectric.

High Q inductor integration

A system and method is described for manufacturing an out of plane integrated circuit inductor. A plurality of parallel metal bars are formed on a substrate and covered with a first passivation layer. A ferromagnetic core is then deposited over the first passivation layer with its length perpendicular to the plurality of parallel metal bars. A second passivation layer is deposited over the ferromagnetic core and vias are etched through the passivation layers to the alternate ends of the underlying parallel metal bars. A plurality of cross connection metal bars are then formed on the second passivation layer with vertical portions that fill the vias and connect the alternate ends of the plurality of parallel metal bars to form an inductor coil. A third passivation layer is then deposited over the cross connection metal bars.

System and method for manufacturing an out of plane integrated circuit inductor

A new IC wafer fabrication process provides an improved CMOS active strip mask, etch, V.sub.T adjust, and gate oxide grow sequence particularly applicable for preparation of CMOS transistors in BICMOS wafers. The new gate oxide process reduces the number of process steps and thermal cycles, increases the reliability of the gate oxide layer, and substantially reduces differential stress and thermal stress related structural silicon defects in the epitaxial silicon. The process proceeds by forming a photoresist CMOS active strip mask exposing CMOS transistor active areas, etching and removing the CVD nitride layer over the CMOS transistor active areas, and leaving the EPIOX layer. Further steps include introducing dopant material through the EPIOX layer into the EPI layer of CMOS transistor active areas with the photoresist active strip mask in place and adjusting the threshold voltage V.sub.T of the CMOS transistors. The invention proceeds by stripping the EPIOX layer over the CMOS transistor active areas without growing a sacrificial oxide SACOX layer, and then removing the photoresist CMOS active strip mask. This step is followed by growing a gate oxide layer over the CMOS transistor active areas using a wet oxide grow process at relatively lower temperature than a dry oxide grow process. Other steps of the invention include forming the combined thicknesses of the CVDSIN and EPIOX layers to provide the control screen necessary for controlling the subsequent base implant to maintain the desired .beta. specification for bipolar transistors. The layers are formed in a thickness ratio CVDSIN/EPIOX in the range of approximately 5/3 or smaller to achieve the desired reduction in silicon defects and increase in current leakage test yield.

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Limington, ME, United States of America

Todd Patrick Thibeault