Intel Corporation

Tahoe Research, Ltd.

Todd M Witter

Nausheen Ansari

Paul S Diefenbaugh

Seh Kwa

Aditya Sreenivas

Maximino Vasquez

Murali Ramadoss

Jason Daniel Tanner

John S Howard

James E Akiyama

Vishal Ravindra Sinha

Arthur Jeremy Runyan

Kathy Bui

Kyungtae Han

Yifan Li

Kim A Meinerth

Zhengmin Li

Ravi Ranganathan

Satish Ramanathan

Joydeep Ray

Altug Koker

David Wyatt

Blaise B Fanning

Eric C Samson

Aditya Navale

David M Puffer

Lakshminarayana Pappu

Tsvika Kurts

Zvika Greenfield

Anant V Nori

Bryan R White

Robert J Johnston

Nadav Bonen

George R Hayek

Gary Smith

Gary K Smith

Sathyamurthi Sadhasivan

Sangeeta Ghangam Manepalli

Tomer Levy

Eran Shifer

Marcelo Yuffe

Ying Cui

Marc D Torrant

Sylvia Downing

Venu Madhav Kuchibhotla

Richard W Jensen

Kristine M Karnos

Sam W Jensen

Sean T Baartmans

Marcus R Winston

Arie Bernstein

Neil Schaper

Zudan Shi

Chandra Mohan Konduru

Eilon Hazan

Rony Ghattas

Gaurav Sutaria

Aswin Padmanabhan

Trudy Hoekstra

Kiran K Velicheti

Seh W Kwa

Maximino Vasques

In one embodiment, a processing device includes a plurality of display interfaces, a plurality of display controllers, and display synchronization circuitry. The display interfaces are used to interface with a plurality of display devices, and the display controllers are used to output video frames to the display devices via the display interfaces. Moreover, the display synchronization circuitry includes a clock synchronization interface and a frame synchronization interface. The clock synchronization interface is used to synchronize a clock rate across the display controllers, while the frame synchronization interface is used to synchronize a frame rate across the display controllers.

Hardware architecture for multi-display video synchronization

Methods, apparatus, systems, and articles of manufacture are disclosed to reduce display connection latency. An example apparatus includes interface circuitry to: detect when a display is plugged into a port; and notify processor circuitry of the detection. In response to the notification, the processor circuitry of the example apparatus moves discrete circuitry into a high power state. The example apparatus also includes discrete circuitry to, while in the high power state, identify the display.

Methods and apparatus to reduce display connection latency

Technology for a display controller is described. The display controller can detect a frame update when the display controller is in a dynamic sleep state. The display controller can wake up from the dynamic sleep state and enter a selective update state at a programmed vertical blanking interrupt (VBI) that precedes an actual VBI. The display controller can perform a scan-out with a display panel during the selective update state. The display controller can return to the dynamic sleep state in a same time frame after the scan-out is completed. The display controller can exclude timing logic to send a VBI at every time frame to the display panel to maintain time synchronization between the display controller and the display panel.

Dynamic sleep for a display panel

Examples described herein relate to a graphics processing system that includes one or more integrated graphics systems and one or more discrete graphics systems. In some examples, an operating system (OS) or other software supports switching between image display data being provided from either an integrated graphics system or a discrete graphics system by configuring a multiplexer at runtime to output image data to a display. In some examples, a multiplexer is not used and interface supported messages are used to transfer image data from an integrated graphics system to a discrete graphics system and the discrete graphics system generates and outputs image data to a display. In some examples, interface supported messages are used to transfer image data from a discrete graphics system to an integrated graphics system and the integrated graphics system uses an overlay process to generate a composite image for output to a display.

Switchable image source in a hybrid graphics systems

Disclosed herein are techniques to provide both asynchronous frame updates and panel self-refresh in a single implementation. A platform can be arranged to provide frame updates asynchronously with the refresh rate of a connected panel while the connected panel can be arranged to self-refresh where no new updates are provided.

Asynchronous single frame update for self-refreshing panels

A processing device comprises a debug port controller to monitor operations of the processing device to determine whether the processing device is operating in a first mode or a second mode and to collect trace information comprising operating characteristics of the processing device. The processing device further comprises a display engine logic to process display data for output to a display device. In addition, the processing device comprises a display engine interface to provide, to a plurality of existing platform connectors, the display data from the display engine logic when the processing device is operating in the first primary mode and the trace information from the debug port controller when the processing device is operating in the second mode as determined by the debug port controller.

High-speed debug port using standard platform connectivity

A processing device comprises an instruction execution unit, a memory agent and pinning logic to pin memory pages in a multi-level memory system upon request by the memory agent. The pinning logic includes an agent interface module to receive, from the memory agent, a pin request indicating a first memory page in the multi-level memory system, the multi-level memory system comprising a near memory and a far memory. The pinning logic further includes a memory interface module to retrieve the first memory page from the far memory and write the first memory page to the near memory. In addition, the pinning logic also includes a descriptor table management module to mark the first memory page as pinned in the near memory, wherein marking the first memory page as pinned comprises setting a pinning bit corresponding to the first memory page in a cache descriptor table and to prevent the first memory page from being evicted from the near memory when the first memory page is marked as pinned.

Isochronous agent data pinning in a multi-level memory system

Techniques for rate governing of a display data stream are described. In one embodiment, for example, an apparatus may comprise a processor circuit and a graphics management module comprising a differential analyzer. In some embodiments, the graphics management module may be operative on the processor circuit to determine a target display data transmission rate for one or more displays, determine, by the differential analyzer, an actual display data transmission rate for one or more display data packets based on the target display data transmission rate, transmit the one or more display data packets based on the actual display data transmission rate, and accumulate a difference between the actual display data transmission rate and the target display data transmission rate for the one or more display data packets. Other embodiments are described and claimed.

Techniques for rate governing of a display data stream

Techniques are described to transmit commands to a display device. The commands can be transmitted in header byte fields of secondary data packets. The commands can be used to cause a target device to capture a frame, enter or exit self refresh mode, or reduce power use of a connection. In addition, a request to exit main link standby mode can cause the target enter training mode without explicit command to exit main link standby mode.

Techniques to transmit commands to a target device to reduce power consumption

A dynamic priority controller monitors a level of data in a display engine buffer and compares the level of data in the display engine buffer to a plurality of thresholds including a first threshold and a second threshold. When the level of data in the display engine buffer is less than or equal to the first threshold, the dynamic priority controller increases a priority for processing display engine data in a communication channel. When the level of data in the display engine buffer is greater than or equal to the second threshold, the dynamic priority controller decreases the priority for processing the display engine data in the communication channel.

Dynamic priority control based on latency tolerance

Techniques are described that can used to synchronize the start of frames from multiple sources so that when a display is to output a frame to a next source, boundaries of current and next source are aligned. Techniques are useful to avoid visual distortions when changing from a first video source to a second video source.

Techniques for aligning frame data

Techniques are described that can used to synchronize the start of frames from multiple sources so that when a display is to output a frame to a next source, boundaries of current and next source are aligned. Techniques attempt to avoid visible glitches when switching from displaying a frame from a first source to displaying frames from a second source even though alignment is achieved by switching if frames that are to be displayed from the second source are similar to those displayed from the first source.

A controller is described that includes wiring to transport notification that a FIFO that holds data to be used to display content on a display has reached a threshold. The controller also includes first control circuitry to turn on a phase locked loop (PLL) circuit to cause logic circuitry within the controller downstream from the PLL to begin to receive a first clock in response to the notification. The logic circuitry is to transport data read from a memory toward the FIFO. The controller also includes second control circuitry to cause the memory to use a second clock provided by the controller in response to the notification.

Low power display mode

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Orangevale, CA, United States of America

Todd M Witter