Wisconsin Alumni Research Foundation

Xerox Corporation

Todd M Austin

Gurindar Singh Sohi

Joseph W Ward

Jeff C Carter

Gregory C Sosinski

Donald L Wegeng

Thomas G Beaman

Dionisios N Pnevmatikatos

The data cache features an improved mechanism for accessing data from the data memory array of a data cache, by generating a predicted address and using it to access the data cache array in parallel with the effective address computation. The logic circuitry consists of elements which are capable of performing a carry-free addition (logical or arithmetic) of a predetermined number of base register address bits with the same number of offset register address bits. Methods to generate and verify the predicted index are also provided.

Data cache fast address calculation system and method

A method for detecting memory access errors which occur while executing a computer program. Spatial and temporal attributes are provided for a data object and these attributes are associated with each pointer to that data object. On a dereference to a pointer, a memory access check is performed which determines (a) whether the dereference falls outside the address range within which valid accesses may be made to the data object, and (b) whether the dereference falls outside the time period within which valid accesses may be made to the data object. If the dereference falls outside the valid address range, a spatial error is flagged. If the dereference falls outside the valid time period, a temporal error is flagged. In addition, a method is described for converting a preexisting source-language program file into a safe program and a method is described for optimizing memory-access checks.

Method for detecting computer memory access errors

An image data transfer architecture in which control data and image data are isolated is provided. Bidirectional buffers isolate data buses from the control bus, thereby allowing control to be maintained by an 8-bit programmed microprocessor. The controller microprocessor does not handle image data thereby reducing complex software and support components required of prior multiple 16- and 32-bit microprocessor controller systems. Isolation is achieved by having multiple data buses handling image data at various stages of processing, such as, for example, input image data, compressed image data and output image data. Additional efficiencies are realized by eliminating the inherent delays caused when high speed image output terminals are forced to share data buses with much lower speed image input terminals.

Image data transfer architecture and method for an electronic

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Madison, WI, United States of America

Todd M Austin