Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Computer Telephony Solutions, Inc.

Todd Lindberg

Robert W Ellis

Kevin M O'Toole

Jacob Schmier

Vivek Shivhare

Atif Hussain

Venugopal Garuda

Jack Frayer

Vidyabhushan Mohan

Andrew David Prosory

Justin Crandall

Skip Welch

Aspects of a storage device including a master chip controller and a slave chip processor and memory including a plurality of memory locations are provided which allow for simplified processing of descriptors associated with host commands in the slave chip based on an adaptive context metadata message from the master chip. When the controller receives a host command, the controller in the master chip provides to the processor in the slave chip a descriptor associated with a host command, an instruction to store the descriptor in the one of the memory locations, and the adaptive context metadata message mapping a type of the descriptor to the one of the memory locations. The processor may then process the descriptor stored in the one of the memory locations based on the message, for example, by refraining from identifying certain information indicated in the descriptor. Reduced latency in command execution may thereby result.

Adaptive context metadata message for optimized two-chip performance

Aspects of a storage device including a memory and a controller are provided which allow for reduction of latency and improve QoS for reads performed in memory locations such as multi-plane dies sharing a bus with the controller. When the controller receives a host read command, the controller sends a read sense command to a memory location to perform a read operation. The controller also sends a status polling command to the memory location to check die status. While the read operation is being performed, and while other read operations are being performed in other memory locations, the controller refrains from polling this memory location and the other memory locations for die status. Rather, the controller continuously toggles a read enable input to the memory location until the read operation is complete and the die status is ready, after which the controller receives data from the memory location.

Read latency reduction through command and polling overhead avoidance

Aspects of a storage device including a controller memory, a die memory, and a plurality of accumulators corresponding to individual DQs are provided for accelerated DQ training and error detection. A controller stores first data in the controller memory, transfers second data to the die memory over an n-bit bus, and receives n bits of the second data from the die memory based on a DQS. The controller then compares n bits of the first data with n bits of the second data to produce n bit results received into respective accumulators, and the controller simultaneously updates different accumulators in response to bit mismatches. During DQ training, if an accumulator value meets a mismatch threshold, the controller modifies a DQS-DQ timing accordingly. During error detection of a read scrambled page, if an accumulator value does not meet an entropy threshold, the controller identifies an error associated with the page.

System for accelerated training of bit output timings

Aspects of a storage device including a memory and a controller are provided which prevent retransmissions of set features commands with identical read voltage threshold offsets for the same die. When the controller receives a first read command for data stored in the memory, the controller identifies a first parameter to modify a first read threshold, and executes a first set features command for modifying the read threshold based on the first parameter. Subsequently, when the controller receives a second read command from the host device for data stored in the memory, the controller identifies a second parameter to modify a second read threshold, and determines whether the first and second parameters are the same. If the parameters are the same, the controller refrains from executing a second set features command for modifying the second read threshold. Thus, the read latency of the storage device may be reduced.

Command optimization through intelligent threshold detection

A memory system comprises a plurality of memory dies and a controller (or other control circuit) connected to the memory dies. To reduce the time it takes for the memory system to program data and make that programmed data available for reading by a host (or other entity), as well as persistently store the data in a compact manner that efficiently uses space in the memory system, the data is concurrently programmed as single bit per memory cell (fast programming) and multiple bits per memory cell (compact storage). To accomplish this programming strategy, the controller concurrently transfers data to be programmed to a first memory die and a second memory die. The transferred data is programmed in the first memory die at a single bit per memory cell and in the second memory die at multiple bits per memory cell.

Non-volatile storage system with reduced program transfers

Systems, methods, and/or devices are used to manage high-priority NAND operations. In some embodiments, the method includes receiving a first command (e.g., requesting a high-priority memory operation) corresponding to a first location (e.g., having both a first physical address and a first aliased physical address) in a first die of a plurality of physical non-volatile memory die in a storage device. If the first die is performing a blocking low-priority memory operation (e.g., the low-priority operation was sent to the first die using a second physical address), the method includes sending a memory operation command, corresponding to the first memory operation, to the first die using the first aliased physical address. In some embodiments, a predefined die-selection portion of the second physical address matches the predefined die-selection portion of the first physical address and does not match the predefined die-selection portion of the first aliased physical address.

High-priority NAND operations management

The various implementations described herein include systems, methods and/or devices used to validate the status of memory operations in a storage device. In one aspect, the method includes sending a first set of command instructions to a first device of the plurality of non-volatile memory devices, including: a memory operation command; a first status polling command to determine a status of the first device, and a second status polling command to determine a status of the first device. The first status polling command is sent after the memory operation command is sent, and the second status polling command is sent after receiving a response to the first status polling command that meets predefined completion criteria. The method further includes forgoing sending any subsequent set of command instructions to the first device until a response to the second status polling command that meets the predefined completion criteria is received.

Validating the status of memory operations

The present invention relates to a system and method for capturing, sharing, annotating, archiving, and reviewing phone calls and related computer video output in a computer document format. The system creates a portable, transferable computer file recording of a phone call & computer video ('phone voice recording,' or 'PVD') that contains attached data to help identify, sort, and archive the file while maintaining the integrity of the file. Another aspect of the invention includes a method of using the system comprising initiating a phone call between two parties; beginning a recording of the call and initiating a PVD for the recording; and terminating the call and creating the PVD for the call. Another aspect of the invention includes a method of accessing a PVD by a user, reviewing and/or modifying the PVD, capturing the modified PVD, and sharing the PVD with another user.

Growing community of inventors

Phoenix, AZ, United States of America

Todd Lindberg