Analog Devices,inc.

Motorola Corporation

Todd L Brooks

Mathew A Rybicki

Lawrence A Singer

David H Robertson

A Paul Brokaw

H Spence Jackson

Evaldo M Miranda

Steve Harston

Anthony Del Muro

Improved data scramblers and swapper cells and improved digital to analog converters are provided. The improved swapper cells permit data to be propagated through the cell immediately upon receipt. The determination of whether to swap data or pass it directly through is based on a history of data values propagated through the cell, but is independent of the values of the particular inputs being swapped. The data scrambler is structured to permit the possible data inputs on swapper cells in the scrambler to be restricted. A minimum delay data scrambler for use in a fast digital to analog converter is disclosed using these components.

Self-linearizing multi-bit DACs

An ADC system includes a sigma-delta modulator that receives an analog input and provides a first digital output and an analog output. An ADC, coupled to the sigma-delta modulator, receives the analog output as an input and provides a second digital output. A digital processor, coupled to the sigma-delta modulator and the ADC, receives the first and second digital outputs and provides a digital representation of the analog input.

High speed sigma-delta analog-to-digital converter system

High-speed sigma-delta ADCs

In a switched-capacitor input sampling structure, a resistor connected in series with the input structure, but after the output of the input switch limits the noise bandwidth of the input structure. The selected placement of the resistor does not appreciably limit the slewing or settling time of downstream circuit elements, resulting in a low noise bandwidth, high speed system.

Low-distortion technique to bandlimit a switched-capacitor sampling

A reference buffer suitable for driving switched-capacitor or resistive load circuits provides a very low output impedance. The reference buffer utilizes an amplifier with a very large and controlled transconductance configured in feedback and compensated by a load capacitance. Cascaded gain stages are used to provide a large, controlled transconductance. In one embodiment, a reference buffer amplifier includes a plurality of voltage gain amplifiers connected in cascade and at least one transconductance amplifier connected to a last-connected of the plurality of voltage gain amplifiers. The amplifier may further include at least one current mirror amplifier connected to the at least one transconductance amplifier. In another embodiment, the reference buffer amplifier includes at least one transconductance amplifier and at least one current mirror amplifier cascade-connected to the at least one transconductance amplifier. The amplifiers can be differential or single-ended.

Reference buffer with multiple gain stages for large, controlled

A two-stage switched-capacitor residue amplifier having novel circuitry in the first and second stages provides fast and accurate settling while configured with a large closed-loop gain, and also provides low power consumption while powered from a five volt supply. The invention is particularly well suited for use in a multi-stage, pipe-lined analog-to-digital converter (ADC) that converts multiple bits in the first pipeline stage. Complementary PMOS and NMOS differential pairs are used in the first and/or second stage to increase the current slew capability of the amplifier. Current mirror gain and/or positive feedback is used in the second stage to increase transonductance and bandwidth. Cascode transistors are used in the output of the first and/or second stages and active cascode gain enhancement is used in the first stage to increase dc gain and accuracy. The common mode level at the output of the second stage is controlled by injecting a pair of control currents (representative of the difference between a common-mode level actually at the output of the second stage and a desired common mode level) into a pair of mirror input nodes in the second stage. The common mode level of the first stage is controlled from a common node of a differential pair of the second stage. The two-stage amplifier of the invention provides a gain bandwidth product of 800 MHz, a closed-loop bandwidth of 50 MHz, a dc gain 90 dB, and a power consumption 80 mW.

Multi-stage high-gain high-speed amplifier

A differential voltage reference circuit implemented in CMOS provides a continuous differential voltage having good substrate and supply noise-rejection and low power consumption. The differential voltage reference is operable under a low voltage power supply in the range of 1-3 volts and does not require a large silicon die area. The differential voltage reference includes two parasitic bipolar transistors and a single differential summing amplifier. PTAT and CTAT differential signals are summed at the amplifier summing junctions to provide a temperature-independent differential reference voltage. The differential amplifier maintains a common-mode level of the output at a constant level with respect to a bias voltage at the bases of the two bipolar transistors.

Low-power differential reference voltage generator

A high-gain, low-power transconductance amplifier suitable for use in switched-capacitor circuits provides improved accuracy and high-speed operation. The transconductance amplifier includes an input circuit that receives an input voltage. A current mirror circuit is coupled to the input circuit. At least one active cascode circuit, coupled to the current mirror circuit, receives current from the current mirror circuit and provides an output current. The active cascode circuit provides gain enhancement to the transconductance amplifier by increasing the output impedance of the transconductance amplifier.

High-gain operational transconductance amplifier offering improved

A low drop-out voltage regulator is compensated by providing a compensation capacitor across an output terminal of the regulator and an output lead of an input stage which compares a reference voltage and a voltage derived from a regulated output signal at the output terminal. The output from the input stage is inverted without gain before being provided to an output stage. This inversion allows Miller compensation with the compensation capacitor.

Frequency compensation for a low drop-out regulator

A current-mode DAC (20) includes two sub-DACs (22, 36), and a calibrated attenuator (48). One sub-DAC (22) receives least-significant-bits (LSB) of a K-bit digital input signal, and the second sub-DAC (36) receives most-significant-bits (MSB) of the K-bit digital input signal. An output of the sub-DAC (22) is attenuated by an attenuator (50), and the attenuated signal is summed with an output of the second sub-DAC (36) to form an analog output signal. A 4-phase gain adjust sample and hold circuit (49) is used to calibrate the attenuator (50). The 4-phase gain adjust sample and hold circuit (49) samples the current from the attenuator (50), and removes device mismatch effects in the attenuator (50) which cause linearity errors in the current-mode DAC (20).

Auto-calibrated current-mode digital-to-analog converter and method

A fully differential line driver circuit (25) includes an input differential amplifier (26) and double-ended differential amplifiers (27, 28). A first output driver stage (29) includes a pair of series connected transistors (30, 31), and a second output driver stage includes a pair of series connected transistors (33, 34). The differential amplifiers (27, 28) provide bias and signals voltages to the gates of the series connected transistors (30, 31, 33, 34). The output stages (29, 32) provide differential output signals for driving a low impedance load. The clamping circuits (35-38) control overlap currents in the output stages (29, 32). Common-mode feedback is used to ensure a common-mode voltage of the differential output signals remains at a predetermined voltage to ensure maximum signal swing and thus, maximum efficiency.

Fully differential line driver circuit having common-mode feedback

A class A amplifier (20) includes an amplifier (21), a capacitor (22), and an output stage (23). The output stage (23) includes a source-follower transistor (24) and a feedback circuit (25). The source-follower transistor (24) receives an analog signal from the amplifier (21) and provides a corresponding output signal to a load. The feedback circuit (25) provides current feedback to maintain a relatively constant drain current in the source-follower transistor (24). The class A amplifier (20) with the feedback circuit (25) provides high current drive capability with low quiescent power consumption, high power supply rejection, high voltage gain, and stable operation without the use of a Miller compensation capacitor.

Amplifier with feedback having high power supply rejection

A self-biased cascode current mirror includes a current mirror (60), and a cascode bias generator (50). The cascode bias generator (50) includes a resistor (51) to provide a bias voltage for the current mirror (60). The current mirror (60) includes cascode transistor (64) and two mirror transistors (62, 63). The bias voltage is approximately equal to a minimum saturation voltage of the cascode transistor (64) plus a gate-source voltage of the transistor (63) of the current mirror (60). The self-biased cascode current mirror (60) has a high output impedance and high voltage swing while providing low power consumption and requiring a small layout area.

Self-biased cascode current mirror having high voltage swing and low

A digital-to-analog converter (10) uses series-connected resistors (55-59) to implement conversion of most significant bits of a digital input signal to an equivalent analog output signal. Current sources (22-26) are used to implement conversion of least significant bits of the digital input signal to the analog output signal. After making a binary-to-thermometer code conversion of the least significant bits, first logic circuitry (70) provides control signals (SI) for controlling the switching of each of the current sources to either a first (42) or a second (44) node. After making a binary to `one of` code conversion of the most significant bits, second logic circuitry (86) provides control signals (SR) for respectively switching the first and second nodes to any two resistor nodes of the resistors. The resistors are connected between a reference voltage terminal and a third node where the analog output signal is developed.

Current/resistor digital-to-analog converter having enhanced integral

A continuous-time differential amplifier (52, 100) preserves fast settling time while reducing a relatively-high offset voltage-normally associated with a continuous-time differential amplifier using MOS load transistors. The differential amplifier (52, 100) includes a first transistor (81) biased as a current source to provide current into emitters of second (82) and third (83) emitter-coupled input transistors. Fourth (84) and fifth (85) load transistors are respectively coupled between collectors of the second (82) and third (83) input transistors and a power supply voltage terminal. An amplifier (70) having a positive input terminal coupled to the collector of the second input transistor (82) and a negative input terminal receiving a bias voltage biases the control electrodes of the load transistors (84, 85). The amplifier (70) increases the effective transconductance of the load transistors (84, 85) to allow larger control electrode areas, which reduces the effect of transistor mismatch.

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Boston, MA, United States of America

Todd L Brooks