Compaq Computer Corporation, Inc.

Todd J Deschepper

Russ Wunderlich

Maria L Melo

Jeffrey T Wilson

Shaun V Wandler

Jeffrey C Stevens

Jeff W Wolford

Khaldoun Alzien

Robert L Woods

Danny Higby

Robert C Elliott

James R Reif

David J Delisle

Walter G Fry

Paul C Stanley

Kamran Khederzadeh

A computer system for supporting a subtractive agent on a secondary PCI bus is provided. A bridge resides between a primary PCI bus and a secondary PCI bus. Where both a master device and a target device reside on the secondary PCI bus, the bridge employs one of two protocols to permit successful completion of the transaction. The protocol used depends upon the type of transaction sought by the master device. Once the subtractive agent is identified by address, the bridge keeps track of its location. Thus, further operations targeting the subtractive agent run without requiring either protocol to be used. Further, the need for a specialized signaling protocol to access the subtractive agent is avoided.

Computer system with support for a subtractive agent on the secondary side of a PCI-to-PCI bridge

A computer system includes a CPU and a memory device coupled by a North bridge logic unit to an expansion bus, such as a PCI bus. A South bridge logic connects to the expansion bus and couples various secondary busses and peripheral devices to the expansion bus. The South bridge logic includes internal control devices or master devices that are designed to run master cycles on the expansion bus. The master devices couple to the expansion bus through a common expansion master interface, which executes master cycles on the expansion bus on behalf of the master devices. The South bridge also includes an internal modular master expansion bus coupling the internal master devices to the common master interface. The internal modular master expansion bus permits the master devices to run master cycles to any expansion bus by understanding a standardized group of signals represented by the internal modular master expansion (IMAX) bus. The master interface then is responsible for understanding the protocol of the expansion bus and converting the IMAX master bus signals to signals compatible with the expansion bus. In addition, a dedicated target IMAX bus may also be provided for coupling internal targets within the South bridge to masters on the expansion bus through a common expansion target interface.

Computer system with bridge logic that includes an internal modular expansion bus and a common master interface for internal master devices

A computer system includes a secondary bus bridge device in a portable computer and a another secondary bus bridge device in an expansion base to which the portable computer connects (docks). A peripheral in the expansion base may initiate a delayed cycle to read or write data to memory through a primary bus bridge device that also couples to a CPU. Both secondary bus bridge devices include an arbiter for controlling arbitration of a peripheral bus that connects both secondary bridge devices. The arbiter in the secondary bridge of the portable computer determines which of the arbiters will have arbitration control of the expansion bus to run cycles. When read data is available, in the case of a delayed read cycle initiated by a peripheral device in the expansion base, the primary bridge strobes a delayed cycle control signal to the arbiter in the portable computer which then gives arbitration control to the arbiter in the expansion base.

Computer system having integrated bus bridge design with delayed transaction arbitration mechanism employed within laptop computer docked to expansion base

A computer system includes a bus bridge which provides an interface between a main memory and a peripheral bus such as a PCI bus. A peripheral bus interface unit is provided which supports delayed transactions. When a PCI bus master effectuates a read cycle to read data from main memory on the PCI bus, the peripheral bus interface detects the read cycle and terminates or retries the transaction on the PCI bus. The peripheral bus interface further requests the read data from main memory and places the read data in a buffer. When the PCI master device re-attempts the read transaction, the peripheral interface provides the read data directly from its delayed read buffer. When the peripheral bus interface retries the PCI master that establishes a delayed read operation, the peripheral bus interface asserts a control signal referred to the delayed cycle signal. A PCI arbiter which controls ownership of the PCI bus receives the delayed cycle signal and, in response to its assertion, lowers a level of arbitration priority provided to the PCI master establishing the delayed read. In one embodiment, the PCI arbiter inhibits ownership of the PCI bus by the master establishing the delayed read in response to assertion of the delayed cycle signal. When the peripheral bus interface receives the read data and is ready to deliver it to the PCI bus, the delayed cycle signal is deasserted (or strobed). The PCI bus arbiter detects this deassertion (or strobing) of the delayed cycle signal and responsively raises a level of arbitration priority to the PCI master establishing the delayed read. In one implementation, upon detecting the deassertion of the delayed cycle signal, the PCI bus arbiter provides a highest level of arbitration priority to the PCI master establishing the delayed read. The delayed read operation then completes when the PCI master re-initiates the read cycle. The optimized arbitration technique may similarly be employed during other delayed transactions, such as memory writes, I/O read or writes, and configuration reads or writes.

Computer system employing optimized delayed transaction arbitration technique

A computer system includes a South bridge logic that connects an expansion bus to one or more secondary expansion busses and peripheral devices. The South bridge logic includes internal control devices that are targets for masters on the expansion bus. The target devices couple to the expansion bus through a common expansion target interface, which monitors and translates master cycles on the expansion bus on behalf of the target devices. The South bridge includes an ACPI/power management logic capable of supporting a Device Idle mode in which selected I/O device may be placed in a low power state. To prevent cycles from being run to a device in a low power state, the ACPI/power management includes status registers that are used to determine when a device in low power mode is the target of an expansion bus cycle. If such a cycle occurs, the cycle is intercepted and an SMI signal is transmitted to the CPU. In addition, the target interface responds to the master by asserting a retry signal. When the transaction is retried, the cycle is passed to the target, which responds with an invalid data signal. The CPU by this time, or at some subsequent time realizes that the target was asleep based upon processing of the SMI signal. The CPU then either re-executes the cycle when the device is removed form the low power state, or else simply rejects the invalid data.

Computer system with bridge logic that asserts a system management interrupt signal when an address is made to a trapped address and which also completes the cycle to the target address

A computer system including a programmable bridge logic device to disable various peripheral device functions is disclosed. The bridge logic device preferably includes an address decoder and one or more peripheral bus controllers. The address decoder preferably includes a configuration disable unit comprising one or more programmable status bits. Each status bit is associated with a particular peripheral device function, such as a IDE or USB functions. When a status bit is set, configuration cycles to the function corresponding to that bit are disabled. In one aspect of the invention, the computer system comprises a laptop computer that can be docked to an expansion base. The laptop and the expansion base may duplicate one or more functions. When docked, the status bit in the bridge device associated with a function also provided in the expansion base is set disabling the duplicate function in the laptop in favor of the function in the expansion base. In this manner, only the peripheral device function in the expansion base is enabled, avoiding confusion to the computer system. When the bridge device receives a configuration cycle targeting a peripheral device function, the address decoder determines whether the status bit associated with that function is set. If the bit is indeed set, indicating that function is disabled in favor of expansion base, the bridge device does not claim the cycle. The CPU, or other device that initiated the cycle determines that the cycle has not been claimed by the bridge device and tries the cycle on the expansion base. If that function is available in the expansion base, then the CPU enables that expansion base peripheral for operation.

Computer system with enhanced docking support

A computer system includes a CPU and a memory device coupled by a North bridge logic unit to an expansion bus, such as a PCI bus. A South bridge logic connects to the expansion bus and couples various secondary busses and peripheral devices to the expansion bus. The South bridge logic includes internal control devices that are targets for masters on the expansion bus. The target devices couple to the expansion bus through a common expansion target interface, which monitors and translates master cycles on the expansion bus on behalf of the target devices. The South bridge also includes an internal modular target expansion bus coupling the internal target devices to the common target interface. The internal modular target expansion bus permits the target devices to receive master cycles from any expansion bus by understanding a standardized group of signals represented by the internal modular target expansion (IMAX) bus. The target interface then is responsible for understanding the protocol of the expansion bus and converting the expansion bus signals to IMAX target bus signals. The IMAX target bus includes both an inbound bus and an outbound data bus for driving out data requested as part of a read cycle to an internal target device.

Computer system with bridge logic that includes an internal modular

A computer system includes an I/O controller and a bridge logic device which transmit status data via a serial bus. The I/O controller comprises an embedded controller, a memory device, and a serial bus interface including a transceiver, a transmit register, and a receiver register. The bridge logic also includes a serial bus interface with a transceiver, a transmit register, and a receiver register. Data is transmitted from the transmit register of one device to the receive register of the other device. Although the serial bus protocol limits data transfers to eight-bit segments, the I/O controller and bridge logic transmit up to twenty-four different variables by encoding each transmitted byte into a data frame that includes a two-bit frame identifier and a six-bit data field. Further, one of the data frames transmitted by the I/O controller includes an acknowledge bit to indicate when a previous frame has been received from the bridge logic. The bridge logic only transmits new data if the I/O controller toggles the acknowledge bit and transmits the frame containing the toggled acknowledge bit to the bridge logic. The acknowledge bit prevents the South Bridge from overwriting previously transmitted data that has not yet been read from the receive register in the I/O controller.

Serial bus system for sending multiple frames of unique data

A computer system includes a South bridge logic device that monitors the FLUSHREQ signal and masks that signal when the CPU transitions the computer to a low power mode of operation. Once masked, the FLUSHREQ cannot be asserted to the North bridge and the conflict between attempts by the CPU and an ISA device to run cycles on the PCI bus is avoided. The South bridge also masks all requests to run cycles on the PCI bus that are not originated by the CPU. The South bridge includes a programmable control register and a PCI arbiter. When a control bit is set in the register, the PCI arbiter waits for FLUSHREQ to be deasserted and then masks FLUSHREQ. The PCI arbiter preferably also disables PCI arbitration by masking all non-CPU. Only the CPU can run PCI cycles when the non-CPU requests are masked. The programmable control register also includes a masking status bit that is set when both the FLUSHREQ and non-CPU request signals are masked by a request mask state machine. The computer system may also include a laptop computer docked to an expansion base with a South bridge included in the computer and the expansion base.

Computer system with improved transition to low power operation

A computer system includes bridge logic that couples peripheral devices to a CPU and main memory and includes power management logic and a programmable interrupt controller. The power management logic includes control logic, a stop clock register, an alternate stop clock register, and a wakeup event register. The operating system initiates a transition to a lower power mode of operation by issuing an IDLE call to the BIOS which responds by configuring a modulation value of 15 into the alternate stop clock register. With a modulation value of 15, the SLEEPREQ signal is continuously asserted disabling the CPU's internal clock. When a subsequent wakeup event occur, an enable bit in the alternate stop clock register is cleared, disabling modulation and deasserting SLEEPREQ. In response to the wakeup event, the amount of SLEEPEQ modulation is changed. Preferably the modulation value is changed to 14 so that SLEEPREQ is asserted for 14 out of every 15 cycles of a 32 KHz clock. The wakeup event register is configured to disable the system timer from being again causing a wakeup event. If a subsequent wakeup event is then detected, either the enable bit in the alternate stop clock register is cleared to disable SLEEPREQ modulation or the modulation value is programmed to a value of 0. If the enable bit is cleared, SLEEPREQ modulation is determined by the modulation value in a secondary stop clock register.

Smart battery power management in a computer system

A computer system includes a CPU and a memory device coupled through a North bridge logic device. The computer also includes a South bridge logic device coupled to the North bridge by a primary bus. The South bridge waits as long as possible before asserting a flush request (FLUSHREQ) control signal to the North bridge. The South bridge asserts the FLUSHREQ signal to the North bridge after a peripheral device coupled to the South bridge requests access to the primary bus to run a cycle. The South bridge first flushes a write queue before asserting the FLUSHREQ signal to the North bridge. In response to the FLUSHREQ control signal, the North bridge flushes one or more of its own internal write queues in preparation for the upcoming peripheral device cycle. By flushing its own internal write queue before asserting FLUSHREQ to the North bridge, the South bridge reduces the amount of time that the CPU will be prevented from accessing the primary expansion bus while the peripheral device attempts to run a cycle on the primary bus. An alternative embodiment of the invention includes a pair of South bridges, one South bridge in a laptop computer and the other South bridge in an expansion base to which the laptop computer mates.

Computer system with bridge logic that reduces interference to CPU

A PCI bridge is configured to perform delayed read operations in response to a memory read initiated on the PCI bus. Normally, the PCI bridge is configured to discard delayed read data read from main memory following a predetermined discard count time after the PCI master establishing the delayed read operation is retried on the PCI bus. The computer system further includes a secondary bus bridge such as an ISA bridge for providing an interface between the PCI bus and an ISA bus. When an ISA device desires to read data from the main memory, the ISA bridge asserts a flush request signal. The PCI bridge responsively flushes any pending CPU to PCI transactions pending within the PCI bridge. When the flushing operation is complete, the PCI bridge asserts an acknowledge signal. A PCI arbiter for arbitrating ownership of the PCI bus may increase a level of arbitration priority provided to the ISA bridge in response to assertion of the acknowledge signal. The PCI bridge is advantageously configured to decrease the time associated with discarding of the delayed read data when the acknowledge signal is asserted.

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Spring, TX, United States of America

Todd J Deschepper