Rca Inc.

Thomson Consumer Electronics Inc.

Rca Licensing Corporation

Hitachi, Ltd.

Todd J Christopher

Russell T Fling

James A Wilber

Donald Henry Willis

Carlos Correa

Charles Benjamin Dieterich

Kevin C Kelleher

Mark D Walby

Donald J Sauer

Eric Douglas Romesburg

William A Lagoni

James Russell Bergen

Shigeru Hirahata

Timothy W Saeger

Ronald Thomas Keen

Karl Francis Horlander

John Alan Hague

Nathaniel H Ersoz

Robert E Morris, Jr

John J Gibson

Albert P Pica

Gerald D Pyles

Gopi N Mehrotra

Tsan H Lin

Eber F Lambert

Ned J Kiser

A first pixel of a given field is compared with second and third vertically aligned pixels of corresponding horizontal position of an adjacent field to produce, for each first pixel, a pixel difference signal having a value of zero if the value of the first pixel is intermediate the values of the second and third pixels, the difference signal otherwise having a value equal to the absolute value of a difference between the value of the first pixel and the value of one of the second and third pixels having a value closest to that of first pixel. The pixel difference signals are accumulated over a predetermined portion of one field period of the video signal to provide a field difference signal which is analyzed by a group of five correlators for patterns characteristic of 2-2 pull-down or 3-2 pull-down film mode sources. Flags are produced for identifying film mode operation and for identifying which of the adjacent fields to use in subsequent video processing such as de-interlacing or flicker reduction.

Method and apparatus for identifying video fields produced by film

Adjustment and maintenance of a phase relationship between a video signal and a scan synchronizing signal to assure proper horizontal centering is provided in a horizontal deflection system. A first phase locked loop generates a first timing signal at a first frequency, synchronously with a horizontal synchronizing component in a video signal. A presettable counting circuit operates synchronously with the first timing signal for dividing a clock signal to generate a second timing signal at a second frequency. A second phase locked loop generates a scan synchronizing signal from the second timing signal. A microprocessor may supply different numbers to a register, the output of the register being coupled to the presettable counting circuit. Different numbers change the relative phase between the first and second timing signals by incremental steps. The microprocessor monitors a video source selection switch to gate one of alternative video sources as a video and synchronizing signal output and adjusts the relative phase between the horizontal synchronizing component of the selected video source and a synchronous timing signal by a factor appropriate for the selected video source. A manually operable circuit may be coupled in a feedback path of the second phase locked loop for adjusting the relative phase between the second timing signal and the scan synchronizing signal, over a range corresponding to an incremental step.

Adjustable video/raster phasing for horizontal deflection system

A binary number is generated representative of net motion during a field interval of an interlaced video signal from which a field to field difference signal is derived having a sign bit and a group of magnitude bits. The magnitude bits are compared with a first threshold to provide a first threshold indicating signal which, with the sign bit, are applied via respective bus lines to each correlator of a group of five correlators. The correlators are addressed using variable modulo addressing to detect patterns representative of 2--2 pull down and 3-2 pull down film originated frames. Logic is provided for detecting when one and only one of the five correlators indicates film detection to verify film mode operation. Error reduction is further enhanced by comparing the field difference signal with a second threshold, higher than the first, to provide a second thresold indicating signal to each correlator via a second bus. Flags are produced for identifying film mode operation and for identifying also which of two adjacent fields are suitable for use in subsequent video processing such as de-interlacing or flicker reduction.

A video signal clamp involves evaluating the difference between the signal level and the desired clamp level during the back porch interval. A correction signal indicates whether the signal level must be increased or decreased to establish the desired clamp level. Generation of the correction signal involves a median filter algorithm. Any required increase or decrease of the signal level occurs continuously throughout each horizontal line interval.

Apparatus for clamping a video signal level

A video signal to be processed is applied to a non-linear processor having an adjustable gain responsive to a control signal over at least one portion of the amplitude range of the video input signal. A sampling circuit, responsive to the video signal, generates video samples related to the video signal. A control circuit, responsive to the video samples, generates the control signal in accordance with the number of samples in at least a given amplitude range thereby controlling the percentage of samples of a given range in displayed images. Plural control and sampling circuits may be included provide control for white stretch processing, black stretch processing and video mid-point processing for enhancing contrast through out the entire video signal range.

Non-linear contrast control apparatus with pixel distribution

A video source provides a temporally interpolated video signal, a spatially interpolated video signal and a motion indicating signal. A difference signal, derived from the temporally and spatially interpolated signals, is symmetrically limited as a function of the motion signal amplitude and then combined with the temporally interpolated signal to form a motion adapted video output signal having (1) reduced motion artifacts such as smearing and loss of fine detail; (2) reduced noise sensitivity; and (3) enhanced low-contrast motion rendition.

Motion adaptive video processing system

Two stage interpolation system

A source responsive to a composite video input signal provides line and burst frequency related timing signals. A measuring circuit responsive to the timing signals provides measurement values which tend to repeat when the video input signal is of a given color television standard and tend to exhibit a pseudo-random distribution otherwise. A histogram processor provides a histogram of the measurements occurring within a given time interval and provides an output signal identifying standard and non-standard video input signal based on the histogram of the measurements.

Apparatus for identifying standard and non-standard video signals

The present invention is directed to a video signal processing system including a burst locked clock generator which is repsonsive to separated chrominance signal provided by a comb filter. The comb filer includes apparatus responsive to a burst gate signal, for passing non-comb filtered video signal during burst intervals thereby enhancing the response time of the clock generator.

Comb filter-burst locked clock circuitry

An input filter separates a luminance input signal into a high frequency component that is noise reduced by coring and a low frequency component that is noise reduced by a frame recursive filter preceded by sub-sampling and followed by sample rate restoration by interpolation. An output circuit combines the noise reduced components to provide a processed output signal in which high frequency portions thereof are subjected to coring and low frequency portions thereof are subjected to recursive filtering. In a specific application the frame recursive filter provides a plurality of low frequency sub-sampled components which are combined with the processed output signal in a further output circuit to provide a noise reduced output signal of progressive scan form.

Dual band progressive television system with noise reduction

Video noise reduction system employing plural frequency bands

Clamping circuitry for adjusting the D.C. voltage of a signal which is A.C. coupled to an ADC includes D.C. level adjusting circuitry coupled to the input of the ADC. Logic circuitry, responsive to a single bit of output samples provided by the ADC, provides control signals to the D.C. level adjusting circuitry, to condition the D.C. level adjusting circuitry to adjust the D.C. level of the A.C. signal to a desired value.

Signal clamp circuitry for analog-to-digital converters

An oscillator includes a mechanical resonator, such as a crystal, and having an amplifier arranged for oscillating at a first frequency. A resonant circuit is coupled in series with the crystal. The resonant circuit is antiresonant at an undesired harmonic frequency of the crystal thus prohibiting oscillation of the oscillator at said undesired harmonic frequency. The present oscillator is a portion of a phase locked loop used in a television receiver for demodulating a composite stereophonic audio signal.

Circuit for preventing VCXO mode jumping

A circuit for receiving a video signal with a horizontal synchronizing component at a horizontal scanning frequency generates an intermediate synchronizing signal synchronized with the horizontal synchronizing component. A horizontal deflection circuit generates horizontal deflection current synchronized with the intermediate synchronizing signal. An oscillator generates a display locked clock signal synchronously with a clock synchronizing signal derived from the horizontal deflection current. A counter divides the clock signal, producing decodable outputs. A decoding circuit generates display locked timing signals, at the frequency of the horizontal synchronizing component and at the frequency of the intermediate signal, from the outputs of the counter. Where the frequency of the intermediate signal is a multiple of the frequency of the horizontal synchronizing component, for example by a factor of two, a circuit coupled to the counter and the decoding circuit associates certain pulses of the display locked clock signal with commencement of video line intervals in the video signal.

Display locked timing signals for video processing

A digital-to-analog converter includes a sampled data sigma-delta modulator to resample and coarsely quantize the digital samples to be converted. The coarsely quantized samples are converted to sequences of pulses which are applied to a pulse sensitive analog integrator to develop analog representations of the digital signal.

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Indianapolis, IN, United States of America

Todd J Christopher