Rockwell Collins, Inc.

Todd E Miller

David J Radack

John L Hagen

Branden H Sletteland

Lloyd F Aquino

Jeff M Henry

Greg L Shelton

Kyle R Peters

Reed A Kovach

Jason L Wong

J Perry Smith

Christopher J Baumler

A system may include a computer readable medium and a processor communicatively coupled to the computer readable medium. The processor may be configured to: obtain a graphical image file, the graphical image file including an image, wherein the image includes a portion including textual characters, wherein each textual character of the textual characters is formed of line segments; and convert the graphical image file to at least one file including hardware directives that when executed cause a recreation of the image of the graphical image file to be drawn, wherein a size of the at least one file is smaller than the graphical image file.

System and method for recreating graphical image using character recognition to reduce storage space

A system and method for verifying cache coherency in a safety-critical avionics processing environment includes a multi-core processor (MCP) having multiple cores, each core having at least an L1 data cache. The MCP may include a shared L2 cache. The MCP may designate one core as primary and the remainder as secondary. The primary core and secondary cores create valid TLB mappings to a data page in system memory and lock L1 cache lines in their data caches. The primary core locks an L2 cache line in the shared cache and updates its locked L1 cache line. When notified of the update, the secondary cores check the test pattern received from the primary core with the updated test pattern in their own L1 cache lines. If the patterns match, the test passes; the MCP may continue the testing process by updating the primary and secondary statuses of each core.

Multi-core cache coherency built-in test

A system and method for detection and correction of single-bit errors in a multi-core processing resource (MCPR) of an avionics processing system includes a RAM EDAC testing module called by the MCPR health monitor to access EDAC registers of a system-on-chip module coupled to the MCPR and access memory addresses passed by the MCPR health monitor to detect single-bit errors. Single-bit errors detected in memory mapped to the hypervisor are corrected by the RAM EDAC testing module. Single-bit errors detected in memory associated with a partition or core of the MCPR are corrected by the health monitor running on the particular partition or core with which the memory portion is associated. Single-bit errors may be detected in unmapped memory associated with a partition or core by accessing the unmapped memory via a temporary TLB entry.

Multi-core RAM error detection and correction (EDAC) test

A multi-core processor system and a method of operating the system allocates fault queues in a shared system memory for each virtual machine of a partitioned guest operating system running on a core or partition of the processor system. Health monitors of the partitioned guest operating system log faults in the fault queue corresponding to the appropriate virtual machine. The health monitors may take additional action in response to warning-level or virtual machine-level faults. A health monitor of the multi-core processor resource then polls each fault queue, as well as the partition-level and module-level event logs maintained by the module operating system, for available faults and logs all faults in a single nonvolatile event log of the multi-core processor resource.

Optimal multi-core health monitor architecture

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Marion, IA, United States of America

Todd E Miller