Impinj, Inc.

Synopsys, Inc.

Virage Logic Corporation

Other

California Institute of Technology

Northrop Grumman Systems Corporation

Trw Limited

Todd E Humes

Christopher J Diorio

Ronald A Oliver

Scott A Cooper

Kurt Eugene Sundstrom

William T Colleran

Alberto Pesavento

Paul F Dietrich

Vadim Gutnik

Chad A Lindhorst

John D Hyde

Frédéric J Bernard

Yanjun Ma

Donald Glen Heflinger

Aanand Esterberg

Jaideep Mavoori

Agustinus Sutandi

Terry D Hass

Miguel E Figueroa

Alex May

Gregory T Kavounas

Andrew Edward Horch

Carver A Mead

Mark Kintis

Bin Wang

Michael H Thomas

James A Roth

Ernest Allen, Iii

Phillip D Hayashida

Amir Sarajedini

Talley J Allen

Dimitri C Desmons

Jeffery S Bauch

Kenneth K Tsai

Jeffrey S Bauch

An RFID integrated circuit, in addition to having conductive pads to electrically couple to an antenna, may also include a conductive bridge configured to electrically connect different portions of the antenna together. In some embodiments, the conductive bridge may be used to form a multi-turn antenna segment.

RFID integrated circuits with electrical bridges

Embodiments are directed to restricting access to Radio Frequency Identification (RFID) tag information based on location. Access to RFID tag information may be restricted at the reader level, at the requester level, and at the network level. When reader-level restrictions exist, devices may be prevented from inventorying tags and retrieving information from tags. When requester-level restrictions exist, a requester or device may be prevented from receiving tag information from inventoried tags or a network. When network-level restrictions exist, a network may discard or otherwise restrict tag information received from devices.

Location-based access to RFID tag information

A Schottky junction diode device having improved performance and a multiple well structure is fabricated in a conventional CMOS process. A substrate including a material doped to a first conductivity type is formed. A first well is disposed over the substrate. The first well includes a material doped differently, such as to a second conductivity type opposite that of the first conductivity type. A second well is disposed within the first well. A region of metal-containing material is disposed in the second well to form a Schottky junction at an interface between the region of metal-containing material and the second well. In one embodiment, a second well contact is disposed in a portion of the second well.

Schottky junction diode devices in CMOS with multiple wells

RFID tags are commanded to generate a pilot tone in their backscatter. When the backscattered pilot tone is received in the reader, the pilot tone is used to estimate the tag period/frequency. Then, the estimate is used to seed and lock a symbol timing recovery loop, which provides a detected signal to one or more correlators for detecting the tag preamble. A delayed version of the received tag signal is compared against a baseline signal threshold established from the received signal to detect the pilot tone.

RFID reader systems detecting pilot tone

Apparatus and systems may include integrated circuits for use with Radio Frequency Identification (RFID) tags having an antenna structure with at least three coupling ends. The integrated circuits may include three or more nodes corresponding respectively to the at least three coupling ends, and a modulator switch to receive a single modulator switching signal input. Methods may include those used to form and operate such circuits. Additional apparatus, systems, and methods are disclosed.

Multiple RF-port modulator for RFID tag

A method of calibrating an oscillator within a Radio-Frequency Identification (RFID) tag includes storing a plurality of calibration values within a memory structure. Each of the calibration values corresponds to a respective oscillation frequency of the oscillator. A selected calibration value is selected from the plurality of calibration values stored, according to a first selection criterion. The oscillator is then calibrated in accordance with the selected calibration value.

Radio-frequency identification tag with oscillator calibration

One Time Programmable (OTP) memory structures and methods for pretesting the support circuitry are provided. A group of dedicated test cells associated with one or more groups of regular OTP cells are used to test the support circuitry for the regular OTP cells. The dedicated cells are programmed and read. The read values are compared to the programmed values or expected values. As a result of the comparison, failing memories may be designated 'Not Usable', while regular OTP cells of passing memories can be programmed for their purpose resulting in elimination of wasted memories during test.

One time programmable memory test structures and methods

A method and apparatus for trimming a high-resolution digital-to-analog converter (DAC) utilizes floating-gate synapse transistors to trim the current sources in the DAC by providing a trimmable current source. Fowler-Nordheim electron tunneling and hot electron injection are the mechanisms used to vary the amount of charge on the floating gate. Since floating gate devices store charge essentially indefinitely, no continuous trimming mechanism is required, although one could be implemented if desired. By trimming the current sources with high accuracy, a DAC can be built with a much higher resolution and with smaller size than that provided by intrinsic device matching.

Apparatus for trimming high-resolution digital-to-analog converter

A semiconductor device is provided that uses a floating gate to store analog- and digital-valued information for periods of time measured in milliseconds to hours. Charge is added to and/or removed from the floating gate by means of direct electron tunneling through the surrounding insulator, with the insulator typically being thin enough such that appreciable tunneling occurs with an insulator voltage smaller than the difference in electron affinities between the semiconductor and the insulator and/or between the floating gate and the insulator. The stored information is refreshed or updated as needed. In many applications, the stored information can be refreshed without interrupting normal circuit operation. Adding and removing charge to or from the floating gate may be performed using separate circuit inputs, to tailor the performance and response of the floating-gate device. There is no need to use a control gate in the floating-gate structures disclosed herein.

Pseudo-nonvolatile direct-tunneling floating-gate device

A Schottky junction diode device having improved performance is fabricated in a conventional CMOS process. A substrate including a material doped to a first conductivity type is formed. A first well is disposed over the substrate. The first well includes a material doped to a second conductivity type opposite that of the first conductivity type. A region of metal-containing material is disposed over the first well to form a Schottky junction at an interface between the region of metal-containing material and the first well. In one embodiment, a first well contact is disposed in a portion of the first well. A second well is disposed over the substrate wherein the second well includes a material doped to the first conductivity type. In one embodiment, the first well and the second well are not in direct contact with one another.

Schottky junction diode devices in CMOS

Adaptive programming methods and supportive device architecture for memory devices are provided. Methods include partitioning words into variable length segments. More particularly, methods include receiving a word of data, parsing the word into a plurality of write-subsets, where the size of the write-subsets depends on values of the data and constraints that are specific to the memory circuit, and writing the data in cells of the memory circuit, one write-subset at a time. A memory device includes a digital controller capable of parsing words into a plurality of write-subsets, where the length of write-subsets are depending on values of the data and constraints that are specific to the memory device.

Adaptive programming of memory circuit including writing data in cells of a memory circuit

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Shoreline, WA, United States of America

Todd E Humes