Lsi Logic Corporation

Nortel Networks Corporation

Avago Technologies General IP (Singapore) Pte. Ltd.

Todd Christopher Mendenhall

Darren Duane Neuman

Manabu Gouzu

Brian Francis Schoner

Jason William Herrick

Gregg Dierke

Yao-Hua Tseng

Manabu Gozu

Katsuhiro Muromachi

A device for multiple-quality level video processing includes a primary tap configured to receive prime-quality video content from a source and to provide the prime-quality video content to a primary path and to a secondary tap. The primary tap may be operable in a prime-quality mode. The secondary tap may be disposed after the primary tap and may be coupled to a number of secondary paths. One or more dithering modules may be disposed after the primary tap. The dithering module(s) may be configured to convert the prime-quality video content provided by the primary tap to lower-bit precision and/or lower pixel-rate video content for use in one or more of the secondary paths.

Parallel pipelines for multiple-quality level video processing

Described are a system and method for providing an interface to synchronize data transfers across clock domains. A first pulse converter receives a request signal in a first clock domain and converts the request signal into a synchronization signal in a second clock domain. A second pulse converter receives the synchronization signal in the second clock domain from the first pulse converter and converts the synchronization signal into an acknowledgment signal in the first clock domain. The pulse converters cooperate thus to perform a self-acknowledging handshake that synchronizes writes and reads to and from a FIFO memory, thereby effectuating the transfer of data across two clock domains.

System and method of cross-clock domain rate matching

A video system is disclosed that processes OSD images and displays the OSD images on a display. At least some of the OSD images are represented by data sets that do not include a color palette. Each OSD data set includes a header comprising multiple bits of status and control information. One of the control bits indicates whether the OSD data set includes a color palette. Preferably that control bit is set to indicate no color palette in present and cleared to indicate the inclusion of a color palette in the OSD data set. By not including a color palette in an OSD data set, the corresponding OSD image can be represented with a smaller data set and can be transferred across a bus with a smaller bandwidth. If the control bit is set, indicating the absence of a color palette in the OSD data set, a color palette included in another OSD data set is used instead to draw the desired OSD image.

On-screen display format reduces memory bandwidth for on-screen display systems

A video filter unit is described which is implemented as a three-stage filter comprising a vertical filter, a horizontal decimation filter, and a horizontal interpolation filter. The three stages of the filter unit preferably connect serially with the vertical filter comprising the input first stage, the horizontal decimation filter comprising the second stage and the horizontal interpolation filter comprising the third stage which provides the output filtered image from the filter unit. As such, the video data to be filtered is provided to the vertical filter which provides its output to the horizontal decimation filter. After horizontal decimation, which can be disabled if desired (i.e., no horizontal decimation), the video data is then horizontally interpolated. The horizontal interpolation filter stage can also be disabled if desired. The vertical filter can be configured to operate either as a decimation filter or an interpolation filter. The vertical filter is a four-tap filter and thus calculates weighted averages of four video values (e.g. luminance values) at a time. The horizontal decimation filter preferably is implemented as a two-tap filter and thus averages two video values at a time. Lastly, the horizontal interpolation filter comprises an eight-tap filter and, accordingly, calculates a weighted average of eight video values.

Digital video filter sequence for bandwidth constrained systems

A video decoder decimates an input image to produce a decimated output image. The video decoder uses approximately every line of pixels in the input image to compute the lines of pixels in the decimated image. The video decoder includes a vertical decimation filter that computes an average, and preferably a weighted average, of luminance (luma) values associated with pixels from each of four lines in the input image. The decimation filter preferably computes a weighted average of lumas from four adjacent lines of pixels from the input image which may represent a frame or a field of video data. The weighted average preferably uses coefficients that weight each luma in the calculation differently. After calculating all of the luma values for a particular line of the decimated image, the line number associated with the first of the four adjacent lines is incremented by four (in a field-based system) to determine the initial line number for calculating the next line in the decimated image. The new initial line number thus represents the first line number of the set of four adjacent lines used to calculate the new line in the decimated image. This technique advantageously results in a high quality decimated image because each line from the initial image is used to compute the decimated image.

Filtering decimation technique in a digital video system

A memory buffer allowing preliminary access to an upstream data portion in a data stream and a method for allowing the access. This memory buffer is a &ldquo;peek-ahead&rdquo; FIFO comprising a data input that receives a data stream, a data output, a circular FIFO buffer that stores data from the input at a circulating read location and provided data from a circulating write location to the data output. The memory buffer also has read and write pointers that indicate the read and write locations in the FIFO buffer. If the upstream data portion is stored in the memory buffer, the read pointer can temporarily advance by an offset number of memory locations to allow reading of the upstream data portion. In one embodiment, this memory buffer is included in a DVD decoder and is used to identify the type of an incoming packet before the entire header of the packet is processed. Also described is a method and system for parsing data words from an interleaved byte stream. The method has steps of: (a) reading a byte from the byte stream, (b) determining a type of the byte, that is&mdash;what type of data is carried in the packet that it comes from, (c) storing the byte in a word-length buffer for its type, (d) transferring the buffer to a word-write memory if the buffer is full, and (e) repeating steps (a)-(d) for subsequent bytes in the data stream.

System for byte packing multiple data channels in an MPEG/DVD system

Peak-ahead FIFO for DVD system stream parsing

A video filter processes pixel data by storing multiple lines of pixel data in a memory buffer and computes a weighted average of the data using a plurality of multipliers and accumulators. The pixel data which, for example, may represent luminance and/or chrominance values is stored in the buffer in an interleaved fashion. Preferably multiple lines of pixel data is stored in a single buffer, thereby reducing the number of traces that would otherwise be required if a separate buffer was used for each line of pixel data.

Vertical filter architecture using interleaved memory for storage of pixel data

A video processing system that processes vertical column of pixels from individual fields is disclosed. The video processing system processes pixels from an even field independent of the pixels in the odd field, and vice versa. The video processing system preferably includes a system memory for storing fields of input video images and a vertical filter coupled to the system memory via a data bus. The field data is retrieved from the system memory by the vertical filter and processed as individual fields. The vertical filter preferably calculates a 2.times. enlargement of the input image, although the filter can be adapted to enlarge by different factors if desired. The enlargement process generally involves representing an input image with twice as many lines of pixels values as the initial image. The values that are used to represent the enlarged pixels are preferably weighted averages of the pixels from an input pixel field. The vertical filter calculates the weighted averages using coefficients that are based on the proximity of the resulting enlarged pixel values to the corresponding pixels from the input field.

Field-based upsampling method for performing zoom in a digital video

A video decoder which uses a dynamic memory allocation scheme having additional buffer read pointers for implementing a freeze mode. The additional buffer read pointers advantageously allow for implementation of a freeze mode on a dynamic memory allocation architecture. In one embodiment, the video decoder includes an MPEG bitstream decoder, FIFO buffer logic, a free segment register, and a display processor. The video decoder decodes an encoded bitstream to obtain image data for storage in an external memory, and the display processor retrieves the image data for display on a monitor. To conserve memory, the bitstream decoder stores only anchor frames as complete images in the external memory, and bi-directional images are stored in dynamically allocated memory segments. Free memory segments are determined by examination of a free segment register, and pointers to the memory segments having image data are passed to the display processor via the FIFO buffers. The display processor removes pointers to memory segments from the FIFO buffers and de-allocates the corresponding memory segments in normal operation. In freeze mode, the display processor leaves the pointers to the memory segments in the FIFO buffer and discontinues the de-allocation. The additional read pointers are used to 'loop' through the pointers held in the FIFO buffer to allow the display to continually re-scan the frozen image.

Video decoder dynamic memory allocation system and method with an

A programmable, byte wise, multimedia bitstream parser comprises an input data organizer, a data management buffer, a register file, a logical unit and a microprogram controller. A data source alternatively provides a bitstream to a parallel or serial port and the input data organizer, which includes a serial to parallel converter and a multiplexer, arranges the incoming data into a parallel stream of bytes for passage to the data management buffer. Status flags are associated with each byte passing through the management buffer to facilitate data processing, including start code and context identification and error handling. The register file includes counters and intermediate data buffers for processing a plurality of layers with data quantities which are not predetermined by syntax. Additionally, the register file is provided in tandem for dual context processing. The microprogram controller is arranged to communicate with the input data organizer, the data management buffer and the register file for the processing of byte wise data. The microprogram controller includes a program on microcode ROM for increased efficiency, accommodation of modifications and debugging, and decreased cost.

Growing community of inventors

San Jose, CA, United States of America

Todd Christopher Mendenhall