Texas Instruments Corporation

Todd Christopher Hiers

Chunhua Hu

Brian Jason Karguth

Chuck Fuoco

Jian Jim Wang

Thanh Thien Tran

Jason Meiners

James E Nave

Ivan Garcia

Xiaodong Wu

Hyunkeun Kim

An address space field is used in conjunction with a normal address field to allow indication of an address space for the particular address value. In one instance, one address space value is used to indicate the bypassing of the address translation used between address spaces. A different address space value is designated for conventional operation, where address translations are performed. Other address space values are used to designate different transformations of the address values or the data. This technique provides a simplified format for handling address values and the like between different devices having different address spaces, simplifying overall computer system design and operation.

Apparatus and mechanism to bypass PCIE address translation by using alternative routing

Apparatus and mechanism to bypass PCIe address translation by using alternative routing

An architecture-specific web-based executable specification tool maintains specification information and metadata for chip and system on a chip (SoC) design. Metadata available in the development ecosystem may be leveraged to improve the specification-to-design process. A unified, integrated environment for subsystem creation, SoC integration, and SoC specification teams is presented using a tool that comprehends SoC constructs. A modern web-based framework (not stand-alone tool) provides collaboration capabilities and allows visual representation and manipulation of data. Connection fabrics (e.g., network on a chip (NoC)) and other project-specific infrastructure can be configured and synthesized on demand and brought in to the design using the common environment. Netlists and other connectivity data can be fed into automated RTL generation processes directly, or used as a reference for implementation design teams. Reports and automated software generation satisfy the needs of the design verification and software teams. Functional and performance testing feedback loops are also provided.

System-on-chip (SoC) assembly, configurable IP generation and IP integration utilizing distributed computer systems

This invention is a video line encapsulation protocol which allows multiple low definition video streams to be combined into a single super frame of high definition video data. Each super frame is formed of individual lines from plural lower definition video input signals. The high definition video frames include meta data in each line identifying the video input source, line and frame. This meta data enables the super frames to be separated into their component input signals within a video processing digital signal processor.

Multichannel video port interface using no external memory

A video port aggregator receives plural asynchronous video data streams. Corresponding input buffers generate video data and a status signal. A memory controller writes the video data in corresponding locations within an external memory. A channel triggers the memory controller to read data out of the external memory for transmission to a single video output port when said corresponding status signal indicates receipt of a predetermined portion of data. This read out of the external memory being faster than the writing. The channel sequencer triggers the memory controller to read data out of the external memory video data of a highest priority asynchronous video data stream having a received next portion of data.

Low-latency multichannel video port aggregator

A system and method for allocating video processing tasks over multiple video processors include an apparatus. The apparatus includes a plurality of video processors. Each video processor includes a first processor that processes video data and manages buffers used in conversion and displaying video data. The video processor includes a second processor that performs video data signal processing and manages buffers used in processing video data. The apparatus also includes a switch coupled to each video processor, as well as video inputs and video outputs. A third processor coupled to the switch, and a memory coupled to each video processor and to the third processor, are also part of the apparatus. The switch selectively couples a video processor to a video input or a video output, the third processor configures the switch based on processing requirements of each video stream, and the memory buffers and stores video data.

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Houston, TX, United States of America

Todd Christopher Hiers