International Business Machines Corporation

University of Texas System

Infineon Technologies Ag

Freescale Semiconductor,inc.

Todd Christopher Bailey

Matthew Earl Colburn

Sidlgata V Sreenivasan

Byung Jin Choi

John G Ekerdt

Byung-Jin Choi

Wai-Kin Li

Allen H Gabor

Colin J Brodsky

Carlton Grant Willson

C Grant Willson

Sajan Marokkey

S V Sreenivasan

Ryan P Deschner

Richard Anthony Conti

Dongbing Shao

Katherina E Babich

Scott David Halle

Ioana C Graur

Marshal A Miller

Daniel S Fischer

Renee Tong Mo

Roger Allan Quon

Daniel J Jaeger

Chandrasekhar Sarma

James Kenyon Schaeffer, Iii

Eric D Luckowski

William M Chu

O Seo Park

William A Muth

Ying H Tsang

Amy L Child

Mattherw E Colburn

SV Sreenivasan

John Ekerdt

John Eckerdt

V Screenivasans S

A photomask lithography simulation model is created for making a semiconductor chip. Poor metrology is filtered and removed from a contour-specific metrology dataset to improve performance of the photomask. Filtering is performed by the application of a weighting scheme.

Process-metrology reproducibility bands for lithographic photomasks

Disclosed herein is an automatic fluid dispensing method and system for dispensing fluid on the surface of a plate-like material, or substrate, including a semiconductor wafer for imprint lithography processes. The dispensing method uses fluid dispenser and a substrate stage that may generate relative lateral motions between a fluid dispenser tip a substrate. Also described herein are methods and devices for creating a planar surface on a substrate using a substantially unpatterned planar template.

Method of automatic fluid dispensing for imprint lithography processes

A method provides improved alignment for a photolithographic exposure. In such method, a first exposure tool and a first chuck used in a reference photolithographic exposure of a first material layer on a substrate can be identified. The substrate typically includes at least a semiconductor layer. The first chuck typically is one of a plurality of chucks usable with the first exposure tool. The method may further include identifying a second exposure tool and a second chuck used in a current photolithographic exposure of a second material layer on the substrate. In one embodiment, alignment correction information specific to each of the identified first exposure tool, the first chuck, the second exposure tool and the second chuck can be used in aligning the semiconductor substrate to a second exposure tool and a second chuck. In one embodiment, such method can compensate for alignment error caused by differences between the first and second exposure tools, between the first and second chucks, or between the first and second exposure tools and between the first and second chucks.

Alignment method for semiconductor processing

A method for edge correction in pattern recognition includes generating a pattern recognition output for a pattern recognition process, including receiving, in the processor, a design layout, receiving a sample plan based on the design layout, receiving a first user-generated edge input, generating a pattern recognition recipe output from the design layout, the sample plan and the user-generated edge input, wherein the pattern recognition recipe output is configured to drive the pattern recognition process, generating a measurement model from the pattern recognition process, generating a measurement model pattern recognition output for an measurement model pattern recognition process, including receiving a second user-generated input and generating a measurement model pattern recognition recipe output from the measurement model and the second user-generated edge input, wherein the measurement model pattern recognition recipe output configured to drive the measurement model pattern recognition process.

Pattern recognition with edge correction for design based metrology

A structure. The structure includes: a hole layer; a hole layer including a top hole layer surface, wherein the hole layer has a thickness in a first direction that is perpendicular to the hole layer surface; a bottom antireflective coating (BARC) layer on and in direct physical contact with the hole layer at the top hole layer surface; a photoresist layer on and in direct physical contact with the BARC layer, wherein a continuous hole in the first direction extends completely through the photoresist layer, the BARC layer, and the hole layer; and a polymerized hole shrinking region in direct physical contact with the photoresist layer at a lateral surface of the photoresist layer and with the hole layer at the top hole layer surface, wherein the hole shrinking region does not extend below the hole layer surface in a direction from the BARC layer to the hole layer.

Structure resulting from chemical shrink process over BARC (bottom anti-reflective coating)

Exemplary embodiments include a method for edge correction in pattern recognition, the method including receiving a design layout, receiving a sample plan based on the design layout, receiving user-generated edge input and generating a recipe output from the design layout, the sample plan and the user-generated edge input. The incorporation of the edge input results in SEM recipes that are much more successful in recognizing patterns that have tendency to deviate in appearance from design by, for example, moderate to severe sidewall angle.

A method and apparatus are described for fabricating metal gate electrodes () over a high-k gate dielectric layer () having a rare earth oxide capping layer () in at least the NMOS device area by treating the surface of a rare earth oxide capping layer () with an oxygen-free plasma process () to improve photoresist adhesion, forming a patterned photoresist layer () directly on the rare earth oxide capping layer (), and then applying a wet etch process () to remove the exposed portion of the rare earth oxide capping layer () from the PMOS device area.

Method of enhancing photoresist adhesion to rare earth oxides

In one embodiment, a method of manufacturing a semiconductor device includes using a processor to generate a first three dimensional (3-D) resist profile for a first process condition using an layout mask of a target structure. The method further includes using a processor to generate a second 3-D resist profile for a second process condition using the layout mask. The first process condition includes a plurality of process variables, and the second process condition includes different values of the plurality of process variables than the first process condition. The method includes generating a 3-D process variable (PV) band profile by combining the first 3-D resist profile with the second 3-D resist profile and displaying a 3-D image of the 3-D PV band profile on a display.

System and method for semiconductor device fabrication using modeling

A lithography system with a stray light feedback system is disclosed. The stray light feedback helps control critical dimension (CD) within a stray light specification limit. A stray light dose control factor is calculated as a function of the stray light measured in the exposure tool and the sensitivity of the resist. The stray light dose control factor is used to adjust the exposure dose to achieve the desired CD. The stray light may be monitored, and if a threshold level of stray light is reached or exceeded, the use of the exposure tool may be discontinued for a particular type of semiconductor product, resist, or mask level, until the lens system is cleaned.

Stray light feedback for dose control in semiconductor lithography systems

A structure and a method for forming the same. The method comprises providing a structure including (a) a hole layer, (b) a BARC (bottom antireflective coating) layer on the top of the hole layer, and (c) a patterned photoresist layer on top of the BARC layer and having a photoresist hole; etching the BARC layer through the photoresist hole to extend the photoresist hole to the hole layer; performing the chemical shrinking process to shrink the extended photoresist hole; and etching the hole layer through the shrunk, extended photoresist hole so as to form a hole in the hole layer.

Method for performing chemical shrink process over BARC (bottom anti-reflective coating)

An imprint lithography template may be used to form an imprinted layer in a light curable liquid disposed on a substrate. During use, the template may be disposed within a template holder. The template holder may include a body with an opening configured to receive the template, a support plate, and an actuator system coupled to the body. The actuator system may be configured to alter a physical dimension of the template during use.

Device for holding a template for use in imprint lithography

Methods of forming a mask for implanting a substrate and implanting using an implant stopping layer with a photoresist provide lower aspect ratio masks that cause minimal damage to trench isolations in the substrate during removal of the mask. In one embodiment, a method of forming a mask includes: depositing an implant stopping layer over the substrate; depositing a photoresist over the implant stopping layer, the implant stopping layer having a density greater than the photoresist; forming a pattern in the photoresist by removing a portion of the photoresist to expose the implant stopping layer; and transferring the pattern into the implant stopping layer by etching to form the mask. The implant stopping layer may include: hydrogenated germanium carbide, nitrogenated germanium carbide, fluorinated germanium carbide, and/or amorphous germanium carbon hydride (GeHX), where X includes carbon. The methods/mask reduce scattering during implanting because the mask has higher density than conventional masks.

Mask forming and implanting methods using implant stopping layer

A method of designing features on a semiconductor wafer. A design of active or functional features is provided for chiplets separated by kerf areas on the wafer. The method then includes determining pattern density of the chiplet features, and applying a pattern of spaced dummy features on chiplet area not covered by active or functional features, as well as in the kerf areas. The dummy features are uniformly expanded or reduced in size until a desired dummy feature pattern density is reached.

Variable fill and cheese for mitigation of BEOL topography

Described are imprint lithography templates, methods of forming and using the templates, and a template holder device. An imprint lithography template may include a body with a plurality of recesses on a surface of the body. The body may be of a material that is substantially transparent to activating light. At least a portion of the plurality of recesses may define features having a feature size less than about 250 nm. A template may be formed by obtaining a material that is substantially transparent to activating light and forming a plurality or recesses on a surface of the template. In some embodiments, a template may further include at least one alignment mark. In some embodiments, a template may further include a gap sensing area. An imprint lithography template may be used to form an imprinted layer in a light curable liquid disposed on a substrate. During use, the template may be disposed within a template holder. The template holder may include a body with an opening configured to receive the template, a support plate, and at least one piezo actuator coupled to the body. The piezo actuator may be configured to alter a physical dimension of the template during use.

Growing community of inventors

Fishkill, NY, United States of America

Todd Christopher Bailey