Freescale Semiconductor,inc.

Motorola Corporation

North Star Innovations Inc.

Todd C Roggenbauer

Ronghua Zhu

Vishnu Khemka

Amitava Bose

Vijay Parthasarathy

Paul Hui

Xiaoqiu Huang

Jiang-kai Zuo

Xu Cheng

Michael C Butner

Yue Fu

Van Wong

A semiconductor process and apparatus provide a high voltage deep trench capacitor structure () that is integrated in an integrated circuit, alone or in alignment with a fringe capacitor (). The deep trench capacitor structure is constructed from a first capacitor plate () that is formed from a doped n-type SOI semiconductor layer (e.g.,-). The second capacitor plate () is formed from a doped p-type polysilicon layer () that is tied to the underlying substrate ().

High voltage deep trench capacitor

A capacitor suitable for inclusion in a semiconductor device includes a substrate, a first metallization level, a capacitor dielectric, a capacitor plate, an interlevel dielectric layer, and a second metallization level. The first metallization level overlies the substrate and includes a first metallization plate overlying a capacitor region of the substrate. The capacitor dielectric overlies the first metallization plate and includes a dielectric material such as a silicon oxide or silicon nitride compound. The capacitor plate is an electrically conductive structure that overlies the capacitor dielectric. The interlevel dielectric overlies the capacitor plate. The second metallization layer overlies the interlevel dielectric layer and may include a second metallization plate and a routing element. The routing element may be electrically connected to the capacitor plate. The metallization plates may include a fingered structure that includes a plurality of elongated elements extending from a cross bar.

Metal-insulator-metal capacitor

An electronic device can include a substrate, a buried insulating layer overlying the substrate, and a semiconductor layer overlying the buried insulating layer, wherein the semiconductor layer is substantially monocrystalline. The electronic device can also include a conductive structure extending through the semiconductor layer and buried insulating layer and abutting the substrate, and an insulating spacer lying between the conductive structure and each of the semiconductor layer and the buried insulating layer.

Electronic device including a conductive structure extending through a buried insulating layer

A dual current path LDMOSFET transistor () is provided which includes a substrate (), a graded buried layer (), an epitaxial drift region () in which a drain region () is formed, a first well region () in which a source region () is formed, a gate electrode () formed adjacent to the source region () to define a first channel region (), and a current routing structure that includes a buried RESURF layer () in ohmic contact with a second well region () formed in a predetermined upper region of the epitaxial layer () so as to be completely covered by the gate electrode (), the current routing structure being spaced apart from the first well region () and from the drain region () on at least a side of the drain region to delineate separate current paths from the source region and through the epitaxial layer.

Dual current path LDMOSFET with graded PBL for ultra high voltage smart power applications

Apparatus and methods are provided for fabricating semiconductor devices with reduced bipolar effects. One apparatus includes a semiconductor body () including a surface and a transistor source () located in the semiconductor body proximate the surface, and the transistor source includes an area () of alternating conductivity regions (). Another apparatus includes a semiconductor body () including a first conductivity and a transistor source () located in the semiconductor body. The transistor source includes multiple regions () including a second conductivity, wherein the regions and the semiconductor body form an area () of alternating regions of the first and second conductivities. One method includes implanting a semiconductor well () including a first conductivity in a substrate () and implanting a plurality of doped regions () comprising a second conductivity in the semiconductor well. An area () comprising regions of alternating conductivities is then formed in the semiconductor well.

MOSFET device including a source with alternating P-type and N-type regions

A process of forming an electronic device can include providing a semiconductor-on-insulator substrate including a substrate, a first semiconductor layer, and a buried insulating layer lying between the first semiconductor layer and the substrate. The process can also include forming a field isolation region within the semiconductor layer, and forming an opening extending through the semiconductor layer and the buried insulating layer to expose the substrate. The process can further include forming a conductive structure within the opening, wherein the conductive structure abuts the substrate.

Process of forming an electronic device including a conductive structure extending through a buried insulating layer

A low leakage bipolar Schottky diode () is formed by parallel lightly doped N () and P () regions adapted to form superjunction regions. First ends of the P regions () are terminated by P+ layers () and second, opposed ends of the N regions () are terminated by N+ layers (). Silicide layers () are provided in contact with both ends of the parallel N and P regions (), thereby forming at the first end ohmic contacts () with the P+ regions () and Schottky contacts () with the N regions) and at the second, opposite end, ohmic contacts () with the N+ regions () and Schottky contacts () with the P regions (). When forward biased current flows in both N () and P () regions thereby reducing the forward drop. When reverse biased, a substantial portion of the voltage is dropped across the lightly doped N () and P () superjunction regions, thereby significantly reducing the reverse leakage.

Bipolar Schottky diode and method

Methods and apparatus are provided for semiconductor device (). The semiconductor device (), comprises a first region () of a first conductivity type extending to a first surface (), a second region () of a second, opposite, conductivity type forming with the first region () a first PN junction () extending to the first surface (), a contact region () of the second conductivity type in the second region () at the first surface () and spaced apart from the first PN junction () by a first distance (L), and a third region (-) of the first conductivity type and of a second length (L), underlying the second region () and forming a second PN junction () therewith spaced apart from the first surface () and located closer to the first PN junction () than to the contact region (). The breakdown voltage is enhanced without degrading other useful properties of the device ().

Variable resurf semiconductor device and method

A microelectronic assembly and a method for constructing a microelectronic assembly are provided. The microelectronic assembly may include a semiconductor substrate with an isolation trench () formed therein. The isolation trench () may have first and second opposing inner walls () and a floor (). First and second conductive plates () may be formed over the first and second opposing inner walls () of the isolation trench () respectively such that there is a gap () between the first and second conductive plates (). First and second semiconductor devices () may be formed in the semiconductor substrate on opposing sides of the isolation trench (). The method may include forming a trench () in a semiconductor substrate, forming first and second conductive plates () within the trench, and forming first and second semiconductor devices () in the semiconductor substrate on opposing sides of the trench ().

Semiconductor device with a multi-plate isolation structure

A semiconductor device may include a semiconductor substrate having a first dopant type. A first semiconductor region within the semiconductor substrate may have a plurality of first and second portions (). The first portions () may have a first thickness, and the second portions () may have a second thickness. The first semiconductor region may have a second dopant type. A plurality of second semiconductor regions () within the semiconductor substrate may each be positioned at least one of directly below and directly above a respective one of the first portions () of the first semiconductor region and laterally between a respective pair of the second portions () of the first semiconductor region. A third semiconductor region () within the semiconductor substrate may have the first dopant type. A gate electrode () may be over at least a portion of the first semiconductor region and at least a portion of the third semiconductor region ().

Semiconductor device and method for forming the same

A power metal-oxide-semiconductor field effect transistor (MOSFET)() incorporates a stepped drift region including a shallow trench insulator (STI)() partially overlapped by the gate () and which extends a portion of the distance to a drain region (). A silicide block extends from and partially overlaps STI () and drain region (). The STI () has a width that is approximately 50% to 75% of the drift region.

Methods and apparatus for a stepped-drift MOSFET

Methods and apparatus are provided for reducing substrate leakage current of RESURF LDMOSFET devices. A semiconductor device comprises a semiconductor substrate () of a first type; first and second terminals () laterally spaced-apart on a surface () above the substrate; a first semiconductor region () of the first type overlying the substrate and ohmically coupled to the first terminal (); a second semiconductor region () of a second opposite type in proximity to the first region and ohmically coupled to the first terminal; a third semiconductor region () of the second type overlying the substrate and ohmically coupled to the second terminal () and laterally arranged with respect to the first region; a parasitic vertical device comprising the first region and the substrate, the parasitic vertical device for permitting leakage current to flow from the first terminal to the substrate; a fourth semiconductor region () of the first type in proximity to the third region and ohmically coupled to the second terminal, thereby forming in combination with the third region a shorted base-collector region of a lateral transistor extending between the first and second terminals to provide diode action; a channel region () of the first type separating the first and third regions at the surface; a gate insulator () overlying the channel region; and a gate electrode () overlying the gate insulator.

Structure and method for RESURF LDMOSFET with a current diverter

A semiconductor deviceis provided. A first layerhas a first dopant type; a second layeris provided over the first layer; and a third layeris provided over the second layer and has the first dopant type. A plurality of first and second semiconductor regionsare within the third layer. The first semiconductor regionhas the first dopant type, and the second semiconductor regionhas the second dopant type. The first and second semiconductor regionsare disposed laterally to one another in an alternating pattern to form a super junction, and the super junction terminates with a final second semiconductor region' of the second dopant type.

Termination structures for super junction devices

A improved MOSFET () has a source () and drain () in a semiconductor body (), surmounted by an insulated control gate () located over the body () between the source () and drain () and adapted to control a conductive channel () extending between the source () and drain (). The insulated gate () is perforated by a series of openings () through which highly doped regions () in the form of a series of (e.g., square) dots () of the same conductivity type as the body () are provided, located in the channel (), spaced apart from each other and from the source () and drain (). These channel dots () are desirably electrically coupled to a highly doped contact () to the body (). The resulting device () has a greater SOA, higher breakdown voltage and higher HBM stress resistance than equivalent prior art devices () without the dotted channel. Threshold voltage is not affected.

Growing community of inventors

Chandler, AZ, United States of America

Todd C Roggenbauer