Sandia Corporation

National Technology & Engineering Solutions of Sandia, LLC

Todd Bauer

Jason Hamlet

Ryan Helinski

Roy H Olsson

Lyndon G Pierson

Peggy J Clews

Michael David Henry

Kenneth Wojciechowski

Thomas A Friedmann

Khalid Mikhiel Hattar

Michael Wiwi

Nathan J Edwards

Thomas M Gurrieri

Blythe G Clark

Sara Jensen Homeijer

Stuart B Van Deusen

Andrew John Gross

David Bruce Burckel

Mark S Derzon

Robert L Jarecki, Jr

Douglas Chandler Trotter

Randolph R Kay

Liam D Claus

Subhash L Shinde

John Teifel

David J Stein

Ryan Michael Birmingham

Andrew Pomerene

Richard S Flores

Nicholas D Pattengale

An article, for example, an integrated circuit (IC), is manufactured such that the article includes an authentication element that is indicative of an authentication code associated with the article. A block of a blockchain ledger is generated based upon the authentication code. After the article leaves a trusted chain of custody, the article can be authenticated based upon the blockchain. An authentication code can be read from an authentication element included in or on an article under test that is of undetermined authenticity. The authentication code can be evaluated against the blockchain to determine if the authentication code is a genuine code used to generate a block of the blockchain. If the authentication code is genuine, the article under test can be authenticated.

Blockchain based integrated circuit authentication

A method for authenticating an additively manufactured (AM) object is disclosed herein. A computing device obtains a measurement that is indicative of a stochastic distribution of dopant incorporated into the AM object. The computing device generates authentication data for the AM object based upon the measurement, and authenticates the AM object based upon the authentication data.

System for authenticating an additively manufactured object

The various technologies presented herein relate to integrating an IC having at least one waveguide incorporated therein with a v-groove array IC such that an optical fiber located in a v-groove is aligned relative to a waveguide in the IC maximizing optical coupling between the fiber and the waveguide. The waveguide IC and the v-groove array IC are bonded in a stacked configuration. Alignment of the waveguide IC and the array IC in the stacked configuration enables advantage to be taken of lithographic accuracy of features formed with respect to the Z-direction. Further, kinematic pins and sockets are utilized to provision accuracy in the X- and Z-directions, wherein advantage is taken of the placement accuracy and fabrication tolerance(s) which can be utilized when forming the and sockets. Accordingly, automated alignment of the waveguide IC and the array IC is enabled, facilitating accurate alignment of the respective waveguides and fibers.

Kinematic chip to chip bonding

Described herein are various technologies pertaining to authentication of integrated circuits by using external factors to affect or modify an output of a physically unclonable function (PUF) circuit. In an example, the output of the PUF circuit in response to a challenge signal can be sensitive to changes in environmental factors. In another example, the output of the PUF circuit can be sensitive to user-selectable configuration parameters of the PUF circuit. In yet another example, the output of the PUF circuit can be modified by additional circuitry external to the PUF circuit based upon one or more selectable or configurable inputs. A PUF-based device authentication system that uses external factors as authentication inputs to affect a challenge response of the device authentication system can enhance authentication capabilities by permitting multi-factor authentication.

Circuit that includes a physically unclonable function

The various technologies presented herein relate to enabling a value generated based upon a physical unclonable function (PUF) response to be available as needed, while also preventing exposure of the PUF to a malicious entity. A masked PUF response can be generated based upon applying a function to a combination of the PUF response and a data file (e.g., a bitstream), and the masked PUF response is forwarded to a requesting entity, rather than the PUF response. Hence, the PUF is masked from any entity requiring access to the PUF. The PUF can be located in a FPGA, wherein the data file is a bitstream pertinent to one or more configurable logic blocks included in the FPGA. A first masked PUF response generated with a first data file can have a different value to a second masked PUF response generated with a second data file.

Repeatable masking of sensitive data

An integrated circuit (IC) based physically unclonable function (PUF) that comprises a common source amplifier for generating PUF output voltages, a unity gain, negative feedback operational amplifier for generating bias voltages, a voltage regulator and a bit exclusion circuit that excludes unstable PUF bits. Compensation circuitry built into the IC-PUF provides a high power supply rejection ratio and enables highly reliable operation of the IC-PUF across varying input voltages and operating temperatures. The IC-PUF generates a uniformly random output bit stream by taking advantage of process variations that are inherent to the fabrication of (metal-oxide semiconductor) MOS transistors.

Integrated circuit physically unclonable function

Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.

Method of making thermally-isolated silicon-based integrated circuits

An apparatus for increasing security in inter-chip communication includes a sending control module, a communication bus, and a receiving control module. The communication bus is coupled between the sending control module and the receiving control module. The sending control module operates to send data on the communication bus, disable the communication bus when threats are detected, or both.

Increasing security in inter-chip communication

Thermally-isolated silicon-based integrated circuits and related methods

A single crystal micromechanical resonator includes a suspended plate of lithium niobate or lithium tantalate. The suspended plate and a support structure are formed from a single crystal.

Single crystal micromechanical resonator

The present invention relates to a single crystal micromechanical resonator. In particular, the resonator includes a lithium niobate or lithium tantalate suspended plate. Also provided are improved microfabrication methods of making resonators, which does not rely on complicated wafer bonding, layer fracturing, and mechanical polishing steps. Rather, the methods allow the resonator and its components to be formed from a single crystal.

Single crystal micromechanical resonator and fabrication methods thereof

The present invention provides methods for etching semiconductor devices, such aluminum nitride resonators. The methods herein allow for devices having improved etch profiles, such that nearly vertical sidewalls can be obtained. In some examples, the method employs a dry etch step with a primary etchant gas that omits BCl, a common additive.

Methods for dry etching semiconductor devices

A 3D stacked sASIC is provided that includes a plurality of 2D reconfigurable structured structured ASIC (sASIC) levels interconnected through hard-wired arrays of 3D vias. The 2D sASIC levels may contain logic, memory, analog functions, and device input/output pad circuitry. During fabrication, these 2D sASIC levels are stacked on top of each other and fused together with 3D metal vias. Such 3D vias may be fabricated as through-silicon vias (TSVs). They may connect to the back-side of the 2D sASIC level, or they may be connected to top metal pads on the front-side of the 2D sASIC level.

Three-dimensional stacked structured ASIC devices and methods of fabrication thereof

An apparatus for detecting radiation is provided. In embodiments, at least one sensor medium is provided, of a kind that interacts with radiation to generate photons and/or charge carriers. The apparatus also includes at least one electrode arrangement configured to collect radiation-generated charge from a sensor medium that has been provided. The apparatus also includes at least one photodetector configured to produce an electrical output in response to photons generated by radiation in such a sensor medium, and an electronic circuit configured to produce an output that is jointly responsive to the collected charge and to the photodetector output. At least one such electrode arrangement, at least one such photodetector, and at least one such sensor medium are combined to form an integral unit.

Multiple-mode radiation detector

Generating a physically a physically unclonable function ('PUF') circuit value includes comparing each of first identification components in a first bank to each of second identification components in a second bank. A given first identification component in the first bank is not compared to another first identification component in the first bank and a given second identification component in the second bank is not compared to another second identification component in the second bank. A digital bit value is generated for each comparison made while comparing each of the first identification components to each of the second identification components. A PUF circuit value is generated from the digital bit values from each comparison made.

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Albuquerque, NM, United States of America

Todd Bauer