University of Michigan

Arm Limited

Microsoft Technology Licensing, LLC

University of Washington

Regents of the U of Michigan

Todd Austin

David Theodore Blaauw

Krisztian Flautner

Trevor N Mudge

David Michael Bull

Valeria Bertacco

Sujay Abhay Phadke

Kypros Constantinides

Smitha Shyam

Dennis Sylvester

Mark Gallagher

Baris Kasikci

John D Davis

Shidhartha Das

Mark Henry Oskin

Timothy Sherwood

Brad Calder

Ilya Wagner

Mojtaba Mehrara

Martha Mercaldi-Kim

Don Yang

Seokwoo Lee

Daniel J Ernst

A computer system includes an ensemble moving target defense architecture that protects the computer system against attack using one or more composable protection layers that change each churn cycle, thereby requiring an attacker to acquire information needed for an attack (e.g., code and pointers) and successfully deploy the attack, before the layers have changed state. Each layer may deploy a respective attack information asset protection providing multiple respective attack protections each churn cycle, wherein the respective attack information asset protections may differ.

Computer system with moving target defenses against vulnerability attacks

A computer system includes an ensemble moving target defense architecture that protects the computer system against attack using a plurality of composable protection layers that change each churn cycle, thereby requiring an attacker to acquire information needed for an attack (e.g., code and pointers) and successfully deploy the attack, before the layers have changed state. Each layer may deploy a different attack information asset protection providing multiple different attack protections each churn cycle.

An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.

Error recovery within integrated circuit

A state matcher for a logic circuit may detect at least one of a buggy state of the logic circuit, a precursor to a buggy state of the logic circuit and a verified state of the logic circuit based on a plurality of signal values indicative of a state of the logic circuit. A recovery controller for a microprocessor may reconfigure the microprocessor to a trusted feature mode in response to receiving a signal indicating that the microprocessor is in a predefined state and operate the microprocessor in the trusted feature mode for a predetermined period of time.

Field repairable logic

An integrated circuit includes a plurality of processing stages each including processing logic, a non-delayed signal-capture element, a delayed signal-capture elementand a comparator. The non-delayed signal-capture elementcaptures an output from the processing logicat a non-delayed capture time. At a later delayed capture time, the delayed signal-capture elementalso captures a value from the processing logic. An error detection circuitand error correction circuitdetect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator. The comparatorcompares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.

Error recover within processing stages of an integrated circuit

A microprocessor has a silicon area comprising a plurality of transistors implemented on the silicon area and a fault detection circuit occupying less than 20% of the silicon area and configured to detect faults at runtime in at least 80% of the plurality of transistors.

Microprocessor and method for detecting faults therein

An integrated circuit includes a plurality of processing stages each including processing logic, a non-delayed signal-capture element, a delayed signal-capture element and a comparator. The non-delayed signal-capture element captures an output from the processing logic at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element also captures a value from the processing logic. An error detection circuit and error correction circuit detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator. The comparator compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.

Error recovery within processing stages of an integrated circuit

A method for detecting microprocessor hardware faults includes sending at least one input signal to a logic block within the microprocessor, collecting an output response to the input signal from the logic block, and determining whether the output response matches an expected output response of the logic block.

An integrated circuithas a specified range of runtime-variable operating parameters. Data processing circuitswithin the integrated circuithave associated error detection and error repair mechanisms. When operating within a narrow typical-case range of runtime-variable operating parameters the data processing circuitsoperate correctly and substantially without error. When operating outside of this typical-case range but inside the specified range of permitted values for the run-time variable operating parameters, then the error detection and error repair circuitoperate to repair the errors which occur.

Growing community of inventors

Ann Arbor, MI, United States of America

Todd Austin