Intel Corporation

Hewlett-packard Development Company, L.p.

Todd Aldridge Dutton

Tryggve Fossum

Daniel William Bailey

George Zacharias Chrysos

Kushagra V Vaid

Joel James McCormack

Robert Stephen McNamara

Bernard Lint

Laura Edwards Mendyke

Alon Naveh

Shivnandan D Kaushik

Jeffrey R Wilcox

Lance E Hacking

Ping Sager

A method and apparatus for heterogeneous chip multiprocessors (CMP) via resource restriction. In one embodiment, the method includes the accessing of a resource utilization register to identify a resource utilization policy. Once accessed, a processor controller ensures that the processor core utilizes a shared resource in a manner specified by the resource utilization policy. In one embodiment, each processor core within a CMP includes an instruction issue throttle resource utilization register, an instruction fetch throttle resource utilization register and other like ways of restricting its utilization of shared resources within a minimum and maximum utilization level. In one embodiment, resource restriction provides a flexible manner for allocating current and power resources to processor cores of a CMP that can be controlled by hardware or software. Other embodiments are described and claimed.

Apparatus and method for heterogeneous chip multiprocessors via resource allocation and restriction

A system, apparatus, and method for a core rationing logic to enable cores of a multi-core processor to adhere to various power and thermal constraints.

Method, system, and apparatus for improving multi-core processor performance

A method and apparatus for global and local power management is herein described. Hardware within monitor/receives power management requests for any number of processing elements and adjusts global performance resources to change the global power state of all the processing elements or adjusts a local performance resource for a processing element to operate that processing element at a pseudo power state within the global power state.

Global and pseudo power state management for multiple processing elements

A mechanism for P-state feedback to operating system (OS) with hardware coordination is described herein. In one embodiment, an example of a process includes, but is not limited to, receiving data from a processor representing an average performance over a previous period of time, and determining a performance state (P-state) for a next period of time based in part on the data representing the average performance over the previous period of time. Other methods and apparatuses are also described.

P-state feedback to operating system with hardware coordination

A method and apparatus for visiting all productive stamp positions for a two-dimensional convex polygonal object. The object is visited with a stamp that has a stamp rectangle, and one or more discrete sample points. A productive location is one for which the object contains at least one of the stamp's sample points when the stamp is placed at that location. An unproductive location is one for which the object contains none of the stamp's sample points when the stamp is placed at that location. Stamp locations are discrete points that are separated vertically by the stamp rectangle's height, and horizontally by the stamp rectangle's width. The stamp may move to a nearby position, or to a previously saved position, as it traverses the object. The stamp moves in such a way as to visit all productive locations for an object while avoiding most of the unproductive locations.

Efficient movement of fragment stamp

A method and apparatus for visiting all stamps that are relevant to a two-dimensional convex polygonal object. The object is visited with a rectangular stamp, which contains one or more discrete sample points. A relevant location is one for which the object contains at least one of the stamp's sample points when the stamp is placed at that location. Stamp locations are discrete points that are separated vertically by the stamp's height, and horizontally by the stamp's width. The stamp may move to a nearby position, or to a previously saved position, as it traverses the object. The plane in which the object lies is partitioned into rectangular tiles, which are at least as wide and high as the stamp. The invention visits stamp locations in an order that respects tile boundaries&mdash;that is, it visits all locations within one tile before visiting any locations within another tile. The invention may also be used with further partitioning of the plane (metatiles), so that it will visit all locations within a metatile before visiting any locations within another metatile, and further visit all locations within a portion of a tile within the current metatile before visiting any locations within a portion of a different tile within the current metatile.

Growing community of inventors

Southborough, MA, United States of America

Todd Aldridge Dutton